Dram cell pair and dram memory cell array

A DRAM memory cell array, comprising:

• memory cells with a storage capacitor and a select transistor having a gate electrode;
• word lines forming in sections a plurality of gate electrodes for selective addressing of the memory cells;
• bit lines coupled to a plurality of the select transistors, for transmitting electric charge stored in the memory cells;
• wherein two of the memory cells are arranged as a DRAM cell pair comprising:
• a trench memory cell comprising:
• a trench capacitor configured as a storage capacitor and formed in oriented fashion at a hole trench that is introduced into a semiconductor substrate from a substrate surface;
• and
• a first select transistor connected to the trench capacitor;
• a stack memory cell comprising:
• a stack capacitor arranged above the substrate surface as storage capacitor;
• and
• a second select transistor connected to the stack capacitor;
• wherein the select transistors each have an active area;
• a first source/drain region coupled to a storage electrode of the respectively associated storage capacitor and formed as a doped region of a first conductivity type;
• a second source/drain region coupled to a bit line for transmitting an electric charge from/to the storage electrode and formed as a doped region of the first conductivity type;
• and
• a channel region configured to space the two source/drain regions apart from one another, and formed as a region that is not doped by the first conductivity type, and the dimensions of which define a channel length and a channel width of the select transistor;
• wherein the two active areas are formed in a semiconductor fin with two parallel longitudinal sides, which is formed as a section of the semiconductor substrate and at one end of which the trench capacitor is arranged;
• and
• wherein the two active areas are arranged one behind the other along a longitudinal axis of the semiconductor fin and are formed in mirror-image fashion with respect to one another, the two source/drain regions of the two select transistors forming a cohesive bit contact terminal region.

A method for fabricating a DRAM memory cell array, comprising:

• introducing trench capacitors, which are arranged so as to form cell rows, and parallel trench isolator structures, which separate two cell rows from one another, into a semiconductor substrate, with semiconductor fins being formed from the semiconductor substrate, which fins are separated from one another at the longitudinal sides by in each case one of the trench isolator structures and at the end sides by in each case one of the trench capacitors;
• providing two gate conductor dots, which are spaced apart from one another and from the end sides of the respective semiconductor fin, on the semiconductor fins;
• defining a bit contact section of the respective semiconductor fin between the two gate conductor dots;
• defining a trench node section of the respective semiconductor fin between the first gate conductor dot and the associated trench capacitor;
• and
• defining a stack node section of the respective semiconductor fin between the second gate conductor dot and the trench capacitor located opposite the associated trench capacitor;
• providing a dielectric gate filling between the gate conductor dots;
• removing first sections of the gate filling above the trench node sections and the trench capacitors by means of a patterning method;
• depositing a contact material;
• selectively causing the contact material to recede at least as far as the top edge of the gate conductor dots, with trench connections, which connect the trench node sections to the storage electrode being formed from the contact material;
• covering the trench connections with a dielectric material;
• forming word lines which intersect the cell rows, with gate conductor dots which are in each case adjacent orthogonally with respect to the cell rows being connected by a continuous connecting layer of the respective word line and the gate filling being supplemented between the word lines;
• removing second sections of the gate filling selectively above the stack node sections and the bit contact sections by means of a patterning method;
• and
• filling the openings which are formed with a contact material, the contact material being used to form lower sections of a bit contact structure, which contact-connects the bit contact sections and connects them to bit lines, and of a stack connection, which contact-connects the stack node sections and connects them to in each case a stack capacitor.

A method for fabricating a DRAM memory cell array, comprising:

• introducing trench capacitors, which are arranged so as to form cell rows, and parallel trench isolator structures which in each case separate two cell rows from one another, into a semiconductor substrate, with semiconductor fins, which are separated from one another at the longitudinal sides by in each case one of the trench isolator structures and at the end sides by in each case one of the trench capacitors, being formed from the semiconductor substrate;
• providing word lines, which have been patterned in strip form and run orthogonally to the cell rows, with in each case two word lines, which are spaced apart from one another and from the end sides of the respective semiconductor fin being formed above each semiconductor fin;
• defining a bit contact section of the semiconductor fin between the two word lines;
• defining a trench node section of the semiconductor fin between the first word line and the associated trench capacitor;
• defining a stack node section of the semiconductor fin between the second word line and a trench capacitor located opposite the associated trench capacitor;
• providing a dielectric gate filling between the word lines;
• removing sections of the gate filling above the bit contact sections and the node sections of the semiconductor fins and above storage electrodes of the trench capacitors by a patterning method;
• depositing a contact material;
• selectively causing the contact material to recede as far as the top edge of the word lines;
• forming lower sections of bit contact structures that which contact-connect the bit contact sections;
• forming lower sections of stack connections that contact-connect the stack node sections;
• forming trench sections that contact-connect the storage electrodes;
• forming node sections, which contact-connect the trench node sections, of trench connections;
• forming strip sections which adjoin the node sections and the trench sections, of the trench connections;
• and
• completing the bit contact structures, which contact-connect the bit contact sections and connect them to bit lines, and the stack connections, which contact-connect the stack node sections and connect them to in each case one stack capacitor.