Semiconductor memory devices including offset active regions

A semiconductor memory device comprising:

• a substrate including a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis, wherein the length is greater than the width, wherein the plurality of active regions are provided in a plurality of columns of active regions in the direction of the second axis;
• a plurality of wordline pairs on the substrate, wherein each wordline pair crosses active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair;
• and
• a plurality of bitlines on the substrate crossing the plurality of wordline pairs, wherein each bitline is electrically coupled to a respective drain portion of an active region of each column, and wherein each bitline is arranged between the respective drain portion and another drain portion of an adjacent active region.

A semiconductor memory device comprising:

• a semiconductor substrate including a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis, wherein the length is greater than the width, wherein the plurality of active regions are provided in a plurality of columns in the direction of the second axis;
• a plurality of wordline pairs on the substrate, wherein each wordline pair crosses active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair;
• and
• a plurality of bitlines on the substrate crossing the plurality of wordline pairs, wherein each bitline is electrically coupled to a drain portion of a respective active region of each column, and wherein each bitline crosses drain portions of active regions of adjacent columns in different directions.

A semiconductor memory device comprising:

• a semiconductor substrate including an active region thereof, wherein the active region has a length and a width, wherein the length is greater than the width;
• a field isolation layer on the semiconductor substrate surrounding the active region;
• first and second wordlines on the substrate and crossing the active region, wherein the first and second wordlines define a drain portion of the active region between the first and second wordlines and first and second source portions of the active region at opposite ends of the active region;
• and
• first and second memory storage elements respectively coupled to the first and second source portions of the active region, wherein the first and second wordlines are between portions of the respective first and second memory storage elements and the substrate in a direction perpendicular to the substrate.