US 2006/0076575 A1Published application

Semiconductor device

AssigneeNEC Electronics Corporation

InventorSadaaki Masuoka

Life of this patent

Estimating the term…

Loading patent…

Abstract

There is provided a semiconductor device in which the thresholds of gate electrodes in transistors can be adjusted together for each of regions having their own functions different from one another. The semiconductor device is provided with: a P-type Si substrate 109; a P-type annular well 181 provided in the element formation surface side of the P-type Si substrate 109; and a N-type annular well 183 provided inside the P-type annular well 181. Moreover, an SRAM-P-type well 185 and an SRAM-N-type well 189 are provided inside the N-type annular well 183. A deep N-type well 133 is provided nearer to the bottom side of the P-type Si substrate 109 than the SRAM-P-type well 185 and the SRAM-N-type well 189. A plurality of P-type wells 103 are provided outside the P-type annular well 181, and a N-type 101 is provided in such a way that the well 101 encloses the outside faces of the P-type wells 103.

A semiconductor device comprising:

a semiconductor substrate of one conductivity type;
a first annular region of one conductivity type, which is formed in an element formation surface side of said semiconductor substrate, and has an annular shape in a plane approximately in parallel with said element formation surface;
a second annular region of a reverse conductivity type, which is formed inside said first annular region in said element formation surface side of the semiconductor substrate, and has an annular shape in a plane approximately in parallel with said element formation surface;
a first region of one conductivity type which is formed inside said second annular region in said element formation surface side of said semiconductor substrate;
a first transistor provided on said first region;
a second region of a reverse conductivity type which is formed inside said second annular region in said element formation surface side of said semiconductor substrate;
a second transistor provided on said second region;
a lower region of a reverse conductivity type, having a configuration in which said lower region is provided nearer to the bottom side of said semiconductor substrate than said first and said second regions, and said first region and the bottom side of said semiconductor substrate are separated from each other;
a plurality of third regions of one conductivity type which are formed outside said second annular region in said element formation surface side of said semiconductor substrate, and are electrically connected to each other through the bottom side of said semiconductor substrate;
a third transistor provided on said third region;
a fourth region of a reverse conductivity type, having a configuration in which said fourth region is formed outside said second annular region in said element formation surface side of said semiconductor substrate, is separated from said second annular region and said lower region by said first annular region, and encloses each of the outside faces of said third regions;
and
a fourth transistor provided on said fourth region.

10 more elements

Facts

Application

11/242,859Filed 5 Oct 2005

Priority

JP 2004-29924513 Oct 2004

Published

13 Apr 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 10/00
Static random access memory [sram] devices
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 84/0191
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their doped wells
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Abstract

Claims5