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US 2006/0069977 A1Published application
Error correction device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsToshinori Maeda, Toru Kakiage
Life of this patent
Estimating the term…
Abstract
In order to reduce the time required for error correction in the error correction device, data are transferred from the buffer memory not only to the syndrome calculator but also to the error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. In the error detection after the error corrector corrects the error, the mid-term results of the error detection obtained before the error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making it possible to execute error detection process at a halfway point.
Claims43
1-6. (canceled)
An error correction device comprising;
- a buffer memory for storing at least one ECC block of data having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to error correction;
- a syndrome calculating means for generating syndrome for data read from said buffer memory;
- an error correcting means for correcting error-containing data in said buffer memory by detecting an error position from the syndrome generated by said syndrome calculating means and by calculating an error value;
- an error detecting means for detecting an error in error-corrected data generated by said error correcting means;
- a bus control means for controlling data transfer between said buffer memory, said syndrome calculating means, said error correcting means, and said error detecting means;
- and a system control means for performing various processes for error correction in predetermined procedures a necessary number of times, wherein
- said system control means comprises:
- a first-time error correction sub means for reading data from said buffer memory in a same direction as calculation for an error detecting code as a first-time error correction;
- for transferring the read data to said syndrome calculating means and to said error detecting means concurrently until said syndrome calculating means detects an error-containing code;
- for making said syndrome calculating means execute syndrome calculation and said error detecting means execute error detection in parallel;
- for making said error correcting means execute error correction when said syndrome calculating means has detected an error-containing code;
- and for making one of said syndrome calculating means and said error correcting means provide the system control means with information which designates a code word containing the error-containing code;
- an even-numbered error correction sub means for reading a code word in a different direction from a preceding odd-numbered error correction;
- for transferring the code word to said syndrome calculating means and to said error detecting means concurrently until said syndrome calculating means detects an error-containing code;
- for making said syndrome calculating means execute syndrome calculation and said error detecting means execute error detection in parallel;
- for making said error correcting means execute error correction when said syndrome calculating means detects an error-containing code;
- and for making said error correcting means provide said system control means with information which designates the position of the error-containing code in an error correcting code word obtained in the error correction;
- a non-error range designating sub means for designating, one sector at a time, a range from which an error-containing code has not been detected at the odd-numbered error correction or the subsequent even-numbered error correction, based on said information that designates the code word including the error-containing code and said information that designates the position of the error-containing code in the error correcting code word;
- an odd-numbered error correction sub means for, as an odd-numbered error correction as a third-time or later error correction, providing concurrently said syndrome calculating means and said error detecting means with a code in the same direction as in the previous odd-numbered error correction except for a sector in one ECC block which has been designated by said non-error range designating sub means as the range from which an error-containing code has not been detected in and before the preceding even-numbered error correction until said syndrome calculating means detects an error-containing code;
- for making said syndrome calculating means execute syndrome calculation and said error detecting means execute error detection in parallel;
- for making said error correcting means execute error correction when said syndrome calculating means detects an error-containing code;
- and for making one of said syndrome calculating means and said error correcting means provide said system control means with information which designates the code word including the error-containing code;
- and
- a number-of-times control sub means for repeating the odd-numbered error correction and the even-numbered error correction a predetermined number of times.
21 more elements
28-30. (canceled)
Dependencies are inferred from the claim text.