Combinatorial at-speed scan testing
AssigneeIntel Corporation
InventorsAtul Athavale, Jason Ng
Life of this patent
Estimating the term…
Abstract
A combinatorial at-speed scan testing. A processor including a plurality of distributed slave counters. Each distributed slave counter coupled to a group of scan chains, each distributed slave counter to generate shift-enable-flop signals to be received by the group of scan chains coupled to each distributed slave counter, the shift-enable-flop signals based at least in part on an external shift-enable signal received by the processor. A scan test controller coupled to the plurality of distributed slave counters to provide control signals to the plurality of distributed slave counters to perform an at-speed test of the processor.
Claims21
A processor, comprising:
- a plurality of distributed slave counters, wherein each distributed slave counter of the plurality of slave counters is coupled to a group of scan chains, each distributed slave counter to generate shift-enable-flop signals to be received by the group of scan chains coupled to each distributed slave counter, the shift-enable-flop signals based at least in part on an external shift-enable signal received by the processor;
- and
- a scan test controller coupled to the plurality of distributed slave counters to provide control signals to the plurality of distributed slave counters to perform an at-speed test of the processor.
A method, comprising:
- shifting in a combinatorial test pattern into scan chains of a processor using a slow-speed clock;
- distributing a shift-enable-flop signal to the scan chains using a plurality of distributed slave counters, each distributed slave counter associated with a group of scan chains, the shift-enable-flop signal based at least in part on a shift-enable signal received at the processor;
- and
- performing an at-speed test of the processor using an at-speed clock of the processor.
A system, comprising:
- an Automatic Test Pattern Generation (ATPG) tool;
- and
- a processor including a combinatorial at-speed scan tester coupled to the ATPG tool, the combinatorial at-speed scan tester including:
- a plurality of consumer flip-flops coupled to a combinatorial circuit of the processor;
- and
- a distributed slave counter coupled to the plurality of consumer flip-flops, wherein the distributed slave counter to generate a shift-enable-flop signal based at least in part on an external shift-enable signal received by the processor from the ATPG tool, the shift-enable-flop signal to be received by the plurality of consumer flip-flops during an at-speed test of the combinatorial circuit.
Dependencies are inferred from the claim text.