Built-in self test circuitry for process monitor circuit for rapidchip and ASIC devices
AssigneeLSI Corporation
InventorsKevin Gearhardt, Anita Greeb
Life of this patent
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Abstract
A test circuitry approach which addresses the shortcoming associated with current process monitor circuitry. The approach provides a means of testing that can be employed in association with any and all tester platforms. On-chip built-in self test (BIST) circuitry is added to the design that analyzes the 10-bit value captured from the counter, and indicates to the ATE via a single pin at a single test vector location whether or not the device has passed its test limits. An alternative solution is to use the digital capture circuitry on a mixed-signal tester to capture the non-deterministic digital word generated by the process monitor circuitry, and then test that result against the desired test limits.
Claims17
Test circuitry for testing the n-bit digital output of a digital output circuit and communicating the result of the test to an external circuit, said test circuitry comprising:
- a first comparator connected to the output of said digital output circuit and configured to test whether the output exceeds a first reference value;
- a second comparator connected to the output of said digital output circuit and configured to test whether the output is less than a second reference value, said test circuitry configured to assess the outputs of the first and second comparators and communicate the result of the test to the external circuit.
Test circuitry on an integrated circuit for testing the n-bit digital output of a process monitor circuit on the integrated circuit and communicating the result of the test to ATE, said test circuitry comprising:
- a first comparator connected to the n-bit digital output of said process monitor circuit and configured to test whether the output exceeds a first reference value;
- a second comparator connected to the n-bit digital output of said process monitor circuit and configured to test whether the output is less than a second reference value, said test circuitry configured to assess the outputs of the first and second comparators and communicate the result of the test to the ATE.
Dependencies are inferred from the claim text.