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US 2006/0069948 A1Published application
Error detecting memory module and method
OwnerJong-Cheol Seo, Byung-Se So +1inventors
InventorsJong-Cheol Seo, Byung-Se So, Young-Man Ahn
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Abstract
We describe and claim an error detecting memory module and method. The module comprises a plurality of memory devices, each memory device to receive an address signal and a command signal from a memory controller, and to detect an error in the address and command signals responsive to an input parity signal. In an embodiment, each memory device is adapted to provide an output parity signal to the memory controller responsive to the detection.
Claims21
A memory module comprising:
- a plurality of memory devices, each memory device to receive an address signal and a command signal from a memory controller, and to detect an error in the address and command signals responsive to an input parity signal.
A memory module comprising:
- a first memory device to receive an address signal and a command signal, and to detect an error in the address and command signals responsive to a first input parity signal;
- and
- a second memory device to receive the address signal and the command signal, and to detect the error in the address and command signals responsive to a second input parity signal.
A method comprising:
- receiving an address signal and a command signal from a memory controller;
- and
- detecting an error in the address and command signals responsive to an input parity signal.
Dependencies are inferred from the claim text.