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US 2006/0069930 A1Published application
Bus architecture with reduced power mode during an access time
AssigneeSeagate Technology LLC
InventorsRobert Dixon, Anthony Priborsky
Life of this patent
Estimating the term…
Abstract
A circuit includes a bus architecture with an active mode and a reduced power mode. A host system provides a request for device data to the bus architecture and a device receives the request during the active mode. The device provides the device data after a device access time. The bus architecture operates in the reduced power mode during the device access time.
Claims20
A circuit, comprising:
- a bus architecture having an active mode and a reduced power mode;
- a host system providing a first transmission of a request for device data to the bus architecture in the active mode;
- and
- a device receiving the request for device data from the bus architecture, the device providing a second transmission of device data to the bus architecture in the active mode after a device access time, the bus architecture operating in the reduced power mode during the device access time.
1 more element
A circuit, comprising:
- a bus architecture having an active mode and a reduced power mode;
- a host system transmitting a request for stored data to the bus architecture in the active mode;
- and
- a data storage device providing a transmission of the stored data to the bus architecture in the active mode after a device access time, the bus architecture operating in the reduced power mode during the device access time.
1 more element
A method of reducing bus power consumption, comprising:
- providing a bus architecture with an active mode and a reduced power mode;
- transmitting a request for device data to the bus architecture in the active mode;
- and
- providing the device data to the bus architecture in the active mode after a device access time, the bus operating in the reduced power mode during the device access time.
1 more element
Dependencies are inferred from the claim text.