Performance enhancement of address translation using translation tables covering large address spaces

A system comprising:

• a memory;
• an input/output (I/O) device generating a guest physical address in a request to access the memory;
• and
• a chipset coupled to the I/O device and the memory, the chipset including a circuit, the circuit comprising:
• a register to store capability indicators to indicate capability supported by the chipset for address translation of the guest physical address to a host physical address, and
• a plurality of multi-level page tables for page walking in the address translation, each of the page tables having page table entries, each of the page table entries having at least an entry specifier corresponding to the capability indicated by the capability indicators.

An article of manufacture comprising:

• a machine-accessible medium including data that, when accessed by a machine, causes the machine to perform operations comprising:
• storing capability indicators in a register to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address;
• and
• walking through a plurality of multi-level page tables in the address translation, each of the page tables having page table entries, each of the page table entries having at least an entry specifier corresponding to the capability indicated by the capability indicators.