Method, system and memory controller utilizing adjustable write data delay settings

A memory controller comprising:

• control transmit circuitry to transmit a control signal to a plurality of memory devices via a shared control signal path;
• data transmit circuitry to transmit data signals to the plurality of memory devices via respective data signal paths;
• and
• timing circuitry to delay transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective memory device of the plurality of memory devices.

A method of controlling memory devices in a system that includes at least a first memory device and a second memory device, the method comprising:

• transmitting a control signal to the memory devices via a control signal path, wherein the control signal propagates past the first memory device and the second memory devices in sequence;
• transmitting a first data signal to the first memory device via a first data signal path after delaying for a first time interval, wherein the first time interval is based, at least in part on a propagation time for the control signal propagating on the control signal path to reach the first memory device;
• and
• transmitting a second data signal to the second memory device via a second data signal path after delaying for a second time interval, wherein the second time interval is based, at least in part on a propagation time for the control signal propagating on the control signal path to reach the second memory device.

A controller device comprising:

• means for transmitting, via a control signal path, a control signal to a first memory device and a second memory device such that the control signal propagates past the first memory device and the second memory device in sequence;
• transmitting a first data signal to the first memory device via a first data signal path after delaying for a first time interval, wherein the first time interval is based, at least in part on a propagation time for the control signal propagating on the control signal path to reach the first memory device;
• and
• transmitting a second data signal to the second memory device via a second data signal path after delaying for a second time interval, wherein the second time interval is based, at least in part on a propagation time for the control signal propagating on the control signal path to reach the second memory device.

A memory system comprising:

• a memory module having a row of memory devices, including a first memory device and a second memory device, and a first termination structure;
• a first data signal path coupled to the first memory device;
• a second data signal path coupled to the second memory device;
• a timing signal path coupled to each of the memory devices and the first termination structure, the timing signal path extending along the row of memory devices such that a timing signal propagating on the timing signal path propagates past each of the memory devices in order before reaching the first termination structure;
• and
• a memory controller, coupled to the memory module, the memory controller having transmit circuitry to transmit write data onto the first data path after a first time delay based, at least in part, on a time required for the timing signal to propagate to the first memory device, and the transmit circuitry to transmit write data onto the second data path after a second time delay based, at least in part, on a time required for the timing signal to propagate to the second memory device.

A system comprising:

• a first memory device including a first memory array
• a second memory device including a second memory array;
• a first signal line coupled to the first memory device, the first signal line to provide first data to be stored in a first location in the first memory array, the first location specified by address information;
• a second signal line coupled to the second memory device, the second signal line to provide second data to be stored in a second location in the second memory array, the second location specified by the address information;
• a third signal line coupled to the first memory device and the second memory device, such that the address information, propagating on the third signal line, propagates past the first memory device before reaching the second memory device;
• and
• a controller including:
• a first circuit to delay transmission of the first data to the first memory device by a first time interval that is based, at least in part, on an amount of time required for the address information propagating on the third signal line to propagate from the memory controller to the first memory device;
• and
• a second circuit to delay transmission of the second data to the second memory device by a second time interval that is based, at least in part, on an amount of time required for the address information propagating on the third signal line to propagate from the memory controller to the second memory device.