De-coupled memory access system and method
AssigneeAnalog Devices, Inc.
InventorsPaul Hollis, George Lattimore, Matthew Rutledge
Life of this patent
Estimating the term…
Abstract
A de-coupled memory access system including a memory access control circuit configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.
Claims29
A de-coupled memory access system comprising:
- a memory access control circuit configured to generate first and second independent, de-coupled time references, said memory access control circuit including:
- a read initiate circuit responsive to said first time reference and a read signal for generating a read enable signal, and
- a write initiate circuit responsive to said second time reference and a write signal for generating a write enable signal independent of said read enable signal for providing independent, de-coupled write access to a memory array.
A memory access control circuit responsive to a clock signal with a predetermined clock cycle for defining an expanded memory access time which is longer than said clock cycle, the memory access control circuit comprising:
- a read initiation circuit responsive to said memory access control circuit for beginning the memory read enable signal within said memory access time but in advance of the clock cycle that defines memory access;
- and
- a write initiation circuit responsive to said memory access control circuit for beginning the memory write enable signal after said read enable signal and within said memory access time.
A de-coupled read and write memory access method, the method comprising the steps of:
- providing first and second time reference signals;
- generating a read enable signal to access a memory array in response to said first time reference and a read initialization signal;
- and
- generating a write enable signal independent of said read enable signal in response to said second time reference and a write signal to provide independent, de-coupled write access to said memory array.
Dependencies are inferred from the claim text.