Memory controller for processor having multiple programmable units
AssigneeIntel Corporation, a Delaware corporation
InventorsWilliam Wheeler, Bradley Burres, Matthew Adiletta, Gilbert Wolrich
Life of this patent
Estimating the term…
Abstract
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
Claims12
1-18. (canceled)
A processor chip, comprising:
- multiple programmable units integrated in the processor chip, wherein at least some of the multiple programmable units integrated in the processor chip comprise multi-threaded programmable units having multiple program counters corresponding to multiple threads of program execution;
- a random access memory controller integrated in the processor chip to couple to an off-chip random access memory, the random access memory controller coupled to the multiple programmable units integrated in the processor chip, the random access memory controller comprising logic to enqueue entries for memory reference requests received from the multiple programmable units into one of multiple queues and select from the enqueued entries to initiate a memory access operation of the off-chip random access memory.
A method of processing network packets, the method comprising:
- executing network packet processing instructions by multiple programmable units integrated in a processor chip, wherein at least some of the multiple programmable units integrated in the processor chip comprise multi-threaded programmable units having multiple program counters corresponding to multiple threads of program execution, at least some of the network packet processing instructions comprising instructions to issue memory reference requests directed to an off-chip random access memory to a random access memory controller integrated on the processor chip;
- and
- receiving the memory reference requests at the random access memory controller integrated in the processor chip;
- enqueuing entries for the received memory reference request;
- and selecting from the enqueued entries to initiate a memory access operation of the off-chip random access memory.
Dependencies are inferred from the claim text.