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US 2006/0069874 A1Published application
Cache organization with an adjustable number of ways
AssigneeIntel Corporation
InventorKiran Desai
Life of this patent
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Abstract
A method and apparatus for an adjustable number of ways within a cache is herein described. A cache may comprise a plurality of lines addressably organized as a plurality of ways, wherein the plurality of ways may be addressably organized as groups. The cache may also have associated cache control logic to map a memory address to at least one way within each group based on a predetermined number of bits in the memory address.
Claims40
A cache comprising:
- a plurality of lines addressably organized as a plurality of ways, wherein the plurality of ways are addressably organized as at least a first group and a second group, and wherein there are a different number of ways addressably organized as the first group than as the second group.
An apparatus comprising:
- a memory array comprising a plurality memory cells, wherein the plurality of memory cells are addressable as a plurality of blocks and wherein the plurality of blocks are addressable as a plurality of groups;
- and
- control logic to map a memory address to at least one block within each of the plurality of groups based on at least a portion of a predetermined number of bits of the memory address.
A cache comprising:
- a first group having a first number of ways, wherein each way has an equal power of two sets;
- a second group having a second number of ways, wherein each way has an equal power of two sets;
- a third group having a third number of ways, wherein each way has an equal power of two sets;
- a fourth group having a fourth number of ways, wherein each way has an equal power of two sets;
- and
- control logic to map an address to at least one way in the first, second, third, and fourth group based on at least a portion of a predetermined number of bits in the memory address.
3 more elements
A system comprising:
- a microprocessor to generate a request, which comprises a virtual memory address, wherein the microprocessor has at least a virtual memory address translation unit to translate the virtual memory address to a physical memory address, an instruction fetch unit to fetch instructions, a decode unit couple to the instruction fetch unit to decode the fetched instructions, and a first level cache comprising a plurality of lines addressable as a plurality of ways, wherein the plurality of ways are addressable as at least a first group and a second group:
- a system memory having a plurality of memory cells, wherein the physical memory address references at least one of the plurality of memory cells;
- and
- cache control logic to receive the microprocessor request and map the physical memory address to at least one way within the first group based on at least a first portion of a predetermined number of bits of the physical memory address and at least one way within the second group based on at least a second portion of the predetermined number of bits of the physical memory address.
1 more element
A method comprising
- requesting an element with an associated address from a memory with a host processor, wherein the host processor has a virtual memory addressing unit;
- reading a predetermined number of bits of the associated address;
- determining at least one of a plurality of ways within a first group and at least one of a plurality of ways within a second group to check if the element is present based on at least a portion of the predetermined number of bits of the associated address;
- and
- checking if the element is present within the at least one determined way in first group and the at least one determined way in the second group.
2 more elements
Dependencies are inferred from the claim text.