Instruction cache using single-ported memories
AssigneeHewlett-Packard Development Company, L.P.
InventorRichard Carlson
Life of this patent
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Abstract
Systems, methodologies, media, and other embodiments associated with cache systems are described. One exemplary system embodiment includes an instruction cache comprising single-ported memories. The example system can further include a cache control logic configured to process cache events of different types that may be received by the instruction cache, and being configured with a multi-stage pipeline that coordinates processing of the cache events to the single-ported memories. The multi-stage pipeline can have different stages pre-assigned as read/write stages for the cache events to minimize access conflicts between the cache events.
Claims30
An instruction cache, comprising:
- single-ported memories;
- a cache control logic configured to process cache events of different types that may be received by the instruction cache, and being configured with a multi-stage pipeline that coordinates processing of the cache events to the single-ported memories;
- and
- the multi-stage pipeline having different stages pre-assigned as read/write stages for the cache events to minimize access conflicts between the cache events.
A computing system, comprising:
- a microprocessor configured to process instructions;
- a single ported cache operably connected to the microprocessor and being configured to store instructions;
- a cache control logic operably connected to the cache and being configured to control cache events into the single ported cache based on a multi-stage pipeline;
- and
- the multi-stage pipeline including stages that define sequences for processing different types of cache events in different stages to minimize access conflicts between the different types of cache events in the single ported cache.
A method for constructing a microprocessor having a cache memory, comprising:
- configuring single ported memories to store addresses and instructions in the cache memory;
- configuring a logic to implement a multi-stage pipeline where operations for performing a set of cache events are assigned to stages in the multi-stage pipeline to minimize access conflicts to the single ported memories;
- and
- operably connecting a cache control logic to the single ported memories where the cache control logic controls processing of the set of cache events using at least the multi-stage pipeline to coordinate a sequence of processing the set of cache events.
A method processing cache events for a single-ported cache, comprising:
- maintaining a pipeline that sequentially cycles through a plurality of stages, the plurality of stages being configured to define a sequence for performing each of the cache events where the sequence minimizes access conflicts between the cache events;
- in response to receiving a cache event, determining when to process the cache event based on the sequence defined by the pipeline;
- and
- processing the received cache event based on at least a current stage of the pipeline and the defined sequence for performing the received cache event.
A system, comprising:
- means for storing contents within an instruction cache and having a single port for accessing the contents;
- means for providing a multi-stage pipeline where operations for performing a set of cache events are associated to stages in the multi-stage pipeline to minimize access conflicts to the memory means;
- and
- means for processing the set of cache events that may be received by the instruction cache using at least the pipeline means to coordinate a processing order of the cache events.
Dependencies are inferred from the claim text.