Enqueueing entries in a packet queue referencing packets

A system, comprising:

• a first memory area;
• a second memory area having a packet queue and a queue descriptor providing information on the packet queue, wherein the queue descriptor includes a pointer referencing one end of the packet queue;
• a third memory area;
• a queue manager enabled to perform operations, the operations comprising:
• (i) adding a packet to the first memory area;
• (ii) writing an entry to the packet queue in the second memory area referencing the added packet;
• (iii) reading the pointer referencing one end of the packet queue from the queue descriptor in the second memory area into the third memory area in one read operation;
• (iv) updating the pointer in the third memory area to point to the added entry in the packet queue;
• and
• (v) writing the updated pointer in the third memory area to the queue descriptor in the second memory area in one write operation.

A network processor, comprising:

• a plurality of packet engines;
• a first and second memory areas in data communication with the packet engines;
• a third memory area;
• a queue manager in one packet engine, wherein the packet engine including the queue manager is in data communication with the second and third memory areas, and wherein the queue manager is enabled to perform operations, the operations comprising:
• (i) adding a packet to the first memory area;
• (ii) writing an entry to the packet queue in the second memory area referencing the added packet;
• (iii) reading the pointer referencing one end of the packet queue from the queue descriptor in the second memory area into the third memory area in one read operation;
• (iv) updating the pointer in the third memory area to point to the added entry in the packet queue;
• and
• (v) writing the updated pointer in the third memory area to the queue descriptor in the second memory area in one write operation.

A network device, comprising:

• a switch fabric;
• and
• a plurality of line cards coupled to the switch fabric, wherein each line card includes a network processor, wherein at least one network processor on the line cards includes:
• (a) a plurality of packet engines;
• (b) a first and second memory areas in data communication with the packet engines;
• (c) a third memory area;
• (d) a queue manager in one packet engine, wherein the packet engine including the queue manager is in data communication with the second and third memory areas, and wherein the queue manager is enabled to perform operations, the operations comprising:
• (i) adding a packet to the first memory area;
• (ii) writing an entry to the packet queue in the second memory area referencing the added packet;
• (iii) reading the pointer referencing one end of the packet queue from the queue descriptor in the second memory area into the third memory area in one read operation;
• (iv) updating the pointer in the third memory area to point to the added entry in the packet queue;
• and
• (v) writing the updated pointer in the third memory area to the queue descriptor in the second memory area in one write operation.

An article of manufacture in communication with a first, second, and third memory areas, wherein the article of manufacture is enabled to cause operations to be performed, the operations comprising:

• maintaining queue descriptor information on a packet queue having entries referencing packets in the first memory area, wherein the queue descriptor information is maintained in the second and third memory areas,
• adding a packet to the first memory area;
• writing an entry to the packet queue in the second memory area referencing the added packet;
• reading a pointer referencing one end of the packet queue from the queue descriptor in the second memory area into the third memory area in one read operation;
• updating the pointer in the third memory area to point to the added entry in the packet queue;
• and
• writing the updated pointer in the third memory area to the queue descriptor in the second memory area in one write operation.