System and method for controlling the access and refresh of a memory

A memory system comprising

• a main memory which must be refreshed to maintain data and which is divided into blocks,
• a cache memory which must be refreshed to maintain data, and which stores selected blocks of information from said main memory, said cache having a valid indicator bit to indicate that the data in said cache is valid data,
• refresh circuitry which is periodically active to refresh said main memory,
• input-output circuitry to write information to a target block in said memory system in response to a write command,
• control circuitry operative when (a) said main memory refresh circuitry is active (b) a write command is received and (c) the data in said cache is data of the target block of said write request, to write said data to said cache, and to refresh said main memory,
• said control circuitry to operative when (a) said main memory refresh circuitry is active (b) a write command is received, and (c) the data in said cache is not data of the memory block to which said write request is directed, to (A) hold the refresh of the target block of the write command and controls the write to the target memory block, (B) refresh the memory blocks other than the target memory block, (C) after the write operation to the target memory block, refreshing the target memory block, (D) if the data in said cache memory is valid data of a memory block other that said target memory block, the data in the cache is written back to said other memory block and the cache is valid bit is disabled.

A method of operating a memory system that includes,

• a main memory which must be refreshed in order to retain data,
• a cache memory which must be refreshed in order to retain data,, said method including the steps of:
• periodically refreshing said main memory and said cache memory in response to main memory refresh and cache memory refresh commands,
• said memory system from time to time receiving memory write commands for initiating memory storage operations and receiving memory read commands for initiating data retrieval operations
• generally giving priority to read or write operations over refresh operations in said main memory, and generally giving priority to the refresh operations over read or write operations in said cache memory,
• delaying the refresh of said cache memory when a memory read command is received, said cache refresh signal is enabled and the data in the cache memory is valid.