Data processing system with bus access retraction

Interconnect circuitry comprising:

• a first master port;
• a second master port;
• a slave port;
• arbiter logic coupled to the first master port, the second master port, and the slave port, the arbiter logic arbitrating access requests from the first and second master ports to the slave port;
• and
• retraction control storage circuitry for storing retraction control information indicating at least one condition under which retraction of an access request is allowed;
• and
• retraction control logic coupled to the arbiter logic and retraction control storage circuitry, the retraction control logic, in response to receiving a retraction request from the arbiter logic, uses the retraction control information to selectively allow retraction of a pending access request previously granted by the arbiter logic based on at least one characteristic of at least one of a pending access request or a subsequently received access request.

A method for access retraction in a data processing system having bus arbitration between a plurality of master ports and at least one slave port, the method comprising:

• storing access retraction control information which indicates at least one condition under which retraction is allowed or disallowed;
• granting a first access request from a first master, corresponding to a first access address, to a first slave port while a second access request, corresponding to a second access address, to the first slave port is in progress;
• after granting the first access request, receiving a third access request from a second master, corresponding to a third access address, to the first slave port;
• requesting retraction of the first access request;
• and
• using the access retraction control information to selectively retract the first access request based on a priority of at least one of the first master and the second master.