Data processing system with bus access retraction
AssigneeFreescale Semiconductor, Inc.
InventorsWilliam Moyer, Jimmy Gumulja, Brett Murdock
Life of this patent
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AssigneeFreescale Semiconductor, Inc.
InventorsWilliam Moyer, Jimmy Gumulja, Brett Murdock
Estimating the term…
A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is beings accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.
A method for access retraction in a data processing system having a bus master and a system bus, the bus master coupled to the system bus, the method comprising:
A method for access retraction in a data processing system having a bus master and a system bus, the bus master coupled to the system bus, the method comprising:
A data processing system, comprising:
In a data processing system having a bus master coupled to a system bus, a method for overriding a bus protocol of the system bus comprising:
A method for access retraction in a data processing system having a bus master and a system bus, the bus master coupled to the system bus, the method comprising:
Dependencies are inferred from the claim text.