Method to mitigate performance turnaround in a bidirectional interconnect
OwnerRandy Osborneinventor
Life of this patent
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Abstract
A memory controller is disclosed. The memory controller includes a mechanism to perform a first command to transition an interface coupled between the memory controller and to facilitate a memory write and to perform a second command to immediately write data to the memory device a predetermined period after performing the command to transition the interface.
Claims21
A method comprising:
- receiving a write command at a memory controller to write to a memory device;
- performing a command to turnaround an interface between the memory controller and the memory device in order to facilitate a memory write;
- and
- performing a command to immediately write data to the memory device at least a predetermined minimum period after performing the command to turnaround the interface.
A computer system comprising:
- a main memory device;
- a bi-directional interface coupled to the main memory device;
- and
- a memory controller, coupled to the bi-directional interface, to perform a first command to turnaround the interface to facilitate a memory write and to perform a second command to immediately write data to the memory device at least a predetermined period after performing the command to turnaround the interface.
(canceled)
The memory controller of claim 98 wherein the second command is similar to a write column address signal with short write latency.
A memory controller comprising a mechanism to perform a first command to turnaround an interface coupled between the memory controller and to facilitate a memory write and to perform a second command to immediately write data to the memory device a predetermined period after performing the command to turnaround the interface.
An article of manufacture including one or more computer readable media that embody a program of instructions, wherein the program of instructions, when executed by a processing unit, causes the processing unit to:
- receive a write command at a memory controller to write to a DRAM;
- perform a command to transition an interface between the memory controller and the DRAM in order to facilitate a memory write;
- and
- perform a command to immediately write data to the DRAM at least a predetermined period after performing the command to transition the interface.
Dependencies are inferred from the claim text.