System and method for introducing dither for reducing spurs in digital-to-time converter direct digital synthesis
AssigneeMotorola, Inc.
InventorsThomas Gradishar, Robert Stengel
Life of this patent
Estimating the term…
Abstract
A direct digital synthesizer (DDS) (300) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (317). The DDS (300) includes one or more dither sources (307) and a random access memory (RAM) (305). The RAM (305) utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source (307) to compensate unequal unit delay values in the DTC (317).
Claims26
A direct digital synthesizer (DDS) including a system for reducing digital-to-time converter (DTC) spurs comprising:
- at least one dither source;
- a random access memory (RAM) including a look-up table for storing delay error values;
- and
- wherein the output of the look-up table is combined with the dither source for compensating unequal unit delay values in the DTC.
A direct digital synthesizer (DDS) that includes a dither source for reducing digital-to-time converter (DTC) spurs comprising:
- a digital source for providing a bit number k;
- a random access memory (RAM) for mapping delay requested by the digital block to a corresponding output delay h;
- an adder for combining the dither source with output delay h to produce a j bit delay number;
- at least one quantizer for rounding the j bit delay number to m+1 bits;
- a modulo for arithmetically manipulating the M+1 bits to m bits;
- supplying an m bit number to the DTC;
- and
- wherein the DDS overcomes the contribution of quantization error and mismatch error based on the m bit number for reducing spurious emissions.
A method for overcoming the contribution of quantization error and mismatch error in a direct digital synthesizer (DDS) comprising the steps of:
- providing a number k that has a predetermined bit width from a digital source;
- supplying the number k as an address to a random access memory (RAM);
- mapping the address from an equally spaced domain to an actual delay value from a DTC;
- combining the actual delay line value with a dither source to provide a number j;
- quantizing the number j to an a delay number m+1 value;
- arithmetically adjusting the number m+1 value to a number m representing delay;
- and
- supplying the number m to a digital-to-time converter (DTC) for reducing DTC spurious emissions of the DDS.
Dependencies are inferred from the claim text.