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AssigneeMicronas GmbH
InventorsDejan Lazich, Herbert Alrutz, Miodrag Temerinac, Steffen Schober
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The invention relates to a method for generating random numbers in which oscillating digital output signals (A1, A2, . . . , AL) of unequal or equal periodicity are generated by at least two ring oscillators (32, 33, 34), an external parity signal (PS) representing a logical state (“0,” “1”) being generated when an odd number of the output signals (A1, A2, . . . , AL) take on a specified logical state (“1”). According to the invention, the external parity signal (PS) is fed back to an external parity input (36, 37, 38) of each of the respective ring oscillators (32, 33, 34). The invention further relates to a random number generator having at least two ring oscillators (32, 33, 34), made up in particular of independently free-running inverter chains with feedback having an odd number (K) of series-connected inverters (inv1,2, inv2,1, inv3,1, . . . , invi,j, . . . , invL,KL) that generate oscillating digital output signals (A1, A2, . . . , AL) of unequal or equal periodicity, and having first parity signal generating means (XOR) that generate an external parity signal (PS) representing a logical state (“0,” “1”) when an odd number of the output signals (A1, A2, . . . , AL) take on a specified logical state (“1”). According to the invention, there are feedback means (xor1, xor2, xor3, xor4, . . . , xorL) that feed back the external parity signal (PS) to an external parity input (36, 37, 38) of each of the respective ring oscillators (32, 33, 34). In this invention the cooperation of chaotic dynamics (feedback of the parity signal) and true randomness (jitter due to thermal noise) in digital circuits, a novel theoretical principle for generating random numbers, has been made into an efficient practical solution.
A method for generating random numbers in which oscillating digital output signals (A1, A2, . . . , AL) of equal or unequal periodicity are generated by at least two ring oscillators, an external parity signal (PS) representing a logical state (“0,” “1”) being generated, which external parity signal takes on the logical state “1” when and only when an odd number of output signals (A1, A2, . . . , AL) exhibit the logical state “1” and takes on the logical state “0” otherwise, wherein the external parity signal (PS) is fed back to an external parity input (36, 37, 38, 45, 46, 47) of each respective ring oscillator.
A random number generator having at least two ring oscillators, made up in particular of independently free-running inverter chains with feedback having an odd number (K) of series-connected inverters (inv1,2, inv2,1, inv3,1, . . . , invi,j, . . . , invL,KL), which generate oscillating digital output signals (A1, A2, . . . , AL) unequal in periodicity, and having first parity signal generating means (XOR), which generate an external parity signal (PS) representing a predetermined logical state (“0,” “1”), which external parity signal takes on the logical state “1” when and only when an odd number of the output signals (A1, A2, . . . , AL) exhibit the logical state “1” and takes on the logical state “0” otherwise, wherein there are feedback means (xor1, xor2, xor3, xor4, . . . , xorL) that feed back the external parity signal (PS) to an external parity input (36, 37, 38, 45, 46, 47) of each of the respective ring oscillators.
Dependencies are inferred from the claim text.