Defect detection using multiple sensors and parallel processing
AssigneeKLA-Tencor Technologies Corporation
InventorsJames Smith, Erik Johnson
Life of this patent
Estimating the term…
Abstract
Techniques for detecting defects on semiconductor wafers are described. The techniques involve a parallel processing system wherein a data distribution system contains data distribution nodes that are interconnected by multiple data transfer paths. This configuration allows data collected by any of the detectors to be routed to any one of a plurality of processing nodes. This in turn allows a variety of defect analysis algorithms to be implemented.
Claims19
A computer-implemented method of detecting features on a semiconductor wafer comprising:
- collecting data with a plurality of detectors that are positioned about the semiconductor wafer, wherein each detector collects one data frame for each of a plurality of device areas;
- transmitting the data frames from each detector to a data distribution node, which is part of a set of data distribution nodes;
- transferring a first data frame along a first data transfer path that connects a first and a second data distribution node;
- transferring a second data frame along a second data transfer path that connects the first and second data distribution nodes;
- routing the data frames from the data distribution nodes to processing nodes, wherein the transferring of data frames between data distribution nodes allows data from any one of the detectors to be routed to any one of the processing nodes;
- processing the data frames within each of the processing nodes, wherein the processing within each processing node includes a composite-row based analysis that involves,
- generating a plurality of first composite images, each of the first composite images being made up of each of the data frames collected by one of the detectors, wherein each data frame corresponds to a respective device area;
- and
- comparing each of the first composite images in order to obtain defect information.
(canceled)
A semiconductor wafer inspection system comprising:
- a semiconductor wafer having a plurality of device areas;
- a plurality of detectors positioned about a semiconductor wafer wherein each detector is configured to collect a data frame for each of the plurality of device areas;
- a data distribution system that includes a plurality of data distribution nodes, at least one of the data distribution nodes configured to receive data frames from the detectors;
- a plurality of data transfer paths connecting each of the data distribution nodes wherein each data transfer path transfers data frames collected by a respective detector;
- a plurality of processing nodes configured to receive data frames from the data distribution system, the processing nodes configured to analyze the data frames, wherein the data transfer paths allow data frames collected by any one of the detectors to be routed to any one of the processing nodes;
- wherein each of the processing nodes are configured to perform a composite-row based analysis that involves,
- generating a plurality of first composite images, each of the first composite images being made up of each of the data frames collected by one of the detectors, wherein each data frame corresponds to a respective device area;
- and
- comparing each of the first composite images in order to obtain defect information.
(canceled)
Dependencies are inferred from the claim text.