Semiconductor device and method for fabricating the same
AssigneeFujitsu Limited
InventorsHirosato Ochimizu, Yasuyoshi Mishima
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Abstract
On an insulation layer 12 formed on a silicon substrate 10, there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34, a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34, a tensile-strained silicon layer 24 formed on the silicon germanium layer 22 and a gate electrode 28 formed on the silicon layer 24 with a gate insulation film 26 formed therebetween and in a PMOS transistor region 20 a PMOS transistor 18 comprising a silicon layer 34, a compression-strained silicon germanium layer formed on the silicon layer 34 and a gate electrode 28 formed on the silicon germanium layer 36 with a gate insulation film 26 formed therebetween.
Claims24
A semiconductor device comprising:
- an insulation layer formed on a substrate;
- a silicon layer formed on the insulation layer;
- a first transistor including a lattice-relaxed silicon germanium layer formed on the silicon layer in a first region, a tensile-strained silicon layer formed on the lattice-relaxed silicon germanium layer and a first gate electrode formed on the tensile-strained silicon layer with a first gate insulation film formed therebetween;
- and
- a second transistor including a compression-strained silicon germanium layer formed on the silicon layer in a second region, and a second gate electrode formed on the compression-strained silicon germanium layer with a second gate insulation film formed therebetween.
A method for fabricating a semiconductor device comprising the steps of:
- forming a lattice-relaxed silicon germanium layer on a silicon layer in a first region, the silicon layer being formed on a substrate with an insulation layer formed therebetween;
- forming a tensile-strained silicon layer on the lattice-relaxed silicon germanium layer;
- and
- forming a compression-strained silicon germanium layer on the silicon layer in a second region,
- an NMOS transistor having the tensile-strained silicon layer as a channel and a PMOS transistor having the compression-strained silicon germanium layer as a channel being formed.
A method for fabricating a semiconductor device comprising the steps of:
- forming a compression-strained silicon germanium layer on a silicon layer formed on a substrate with an insulation layer formed therebetween;
- and
- applying an energy beam to the compression-strained silicon germanium layer to lattice-relax the compression-strained silicon germanium layer.
Dependencies are inferred from the claim text.