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US 2006/0068548 A1Published application
Memory cell and method for forming the same
AssigneeMicron Technology, Inc.
InventorKris Brown
Life of this patent
Estimating the term…
Abstract
A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.
Claims52
1-25. (canceled)
A memory device having an address bus and a data terminal, comprising:
- an array of memory cells formed on a substrate having a surface, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
- a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
- a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus;
- and
- a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein a plurality of memory cells of the array of memory cells comprises:
- an active region formed in the substrate;
- a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;
- a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;
- a plurality of memory cell capacitors formed on a respective one of the plurality of posts;
- and
- a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region.
8 more elements
A memory device having an address bus and a data terminal, comprising:
- an array of memory cells formed on a substrate having a surface, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
- a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
- a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus;
- and
- a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell of the array of memory cells comprises:
- an active region formed in the substrate;
- a semiconductor post formed on the active region;
- first and second contacts formed on the active region and on laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;
- a memory cell capacitor formed on the semiconductor post;
- and
- a vertical access transistor having a gate formed adjacent the semiconductor post and configured to electrically couple the capacitor to the first and second contacts in response to being activated.
8 more elements
A computer system, comprising:
- a processor having a processor bus;
- an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
- an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system;
- and
- a memory device coupled to the processor through the processor bus, the memory device comprising:
- an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
- a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
- a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus;
- and
- a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein a plurality of memory cells of the array of memory cells comprises:
- an active region formed in the substrate;
- a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;
- a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;
- a plurality of memory cell capacitors formed on a respective one of the plurality of posts;
- and
- a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region.
13 more elements
A computer system, comprising:
- a processor having a processor bus;
- an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
- an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system;
- and
- a memory device coupled to the processor through the processor bus, the memory device comprising:
- an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
- a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
- a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus;
- and
- a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell of the array of memory cells comprises:
- an active region formed in the substrate;
- a semiconductor post formed on the active region;
- first and second contacts formed on the active region and on laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;
- a memory cell capacitor formed on the semiconductor post;
- and
- a vertical access transistor having a gate formed adjacent the semiconductor post and configured to electrically couple the capacitor to the first and second contacts in response to being activated.
13 more elements
76-100. (canceled)
Dependencies are inferred from the claim text.