Method for operating an MFIS ferroelectric memory array
AssigneeSharp Laboratories of America, Inc.
InventorsSheng Hsu, Fengyan Zhang, Tingkai Li
Life of this patent
Estimating the term…
Abstract
An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.
Claims10
1-15. (canceled)
A method of block erasing an MFIS memory array comprising:
- providing the MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ regions and are further joined to a P+ substrate region on an SOI substrate;
- and
- applying a negative programming voltage to the word line while simultaneously holding all bit outputs along the word line, the common source, and the P+ substrate region at ground.
A method of programming a selected bit within an MFIS memory array comprising:
- providing the MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ regions and are further joined to a P+ substrate region on an SOI substrate;
- and
- holding the selected bit at ground and applying a pulsed positive programming voltage to a selected word line, while simultaneously applying a portion of the positive programming voltage to all unselected bit lines, all unselected word lines and all sources, and holding the P+ substrate region at ground.
Dependencies are inferred from the claim text.