Method for fabricating carrier structure integrated with semiconductor element
AssigneePhoenix Precision Technology Corporation
InventorChi-Ming Chen
Life of this patent
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Abstract
A method for fabricating a carrier structure integrated with a semiconductor element is proposed. First, a carrier having at least one opening therein is provided, and at least one semiconductor element is embedded in the opening. Then, a photosensitive insulating layer is formed on the carrier and filled into a gap between the opening of the carrier and the semiconductor element, such that the semiconductor element is fixed in the opening. Subsequently, the photosensitive insulating layer is patterned, and build-up circuits are formed on the semiconductor element. By such arrangement, the overall fabrication processes are simplified and the fabrication cost can be reduced.
Claims14
A method for fabricating a carrier structure integrated with a semiconductor element, comprising the steps of:
- providing a carrier having at least one opening therein, the carrier having an upper surface and a lower surface;
- embedding at least one semiconductor element in the opening of the carrier;
- and
- forming a photosensitive insulating layer over the upper surface of the carrier, and filling the photosensitive insulating layer into a gap between the opening of the carrier and the semiconductor element, such that the semiconductor element is fixed in the opening.
A method for fabricating a carrier structure integrated with a semiconductor element, comprising the steps of:
- providing a carrier having at least one opening therein, the carrier having an upper surface and a lower surface;
- embedding at least one semiconductor element in the opening of the carrier;
- forming a first photosensitive insulating layer over the upper surface of the carrier, and filling the first photosensitive insulating layer into a gap between the opening of the carrier and the semiconductor element, such that the semiconductor element is fixed in the opening;
- performing a patterning process on the first photosensitive insulating layer to form a plurality of recessed grooves in the first photosensitive insulating layer, such that electrode pads of the semiconductor element and predetermined portions of the carrier are exposed via the recessed grooves;
- forming a seed layer over the first photosensitive insulating layer and in the recessed grooves, wherein the seed layer is connected to the electrode pads of the semiconductor element;
- forming a second photosensitive insulating layer on the seed layer;
- patterning the second photosensitive insulating layer, so as to allow the recessed grooves having the seed layer therein to be exposed from the patterned second photosensitive insulating layer;
- forming a build-up circuit respectively in the recessed grooves via the seed layer by an electroplating process;
- and
- removing the second photosensitive insulating layer and the seed layer covered by the second photosensitive insulating layer.
Dependencies are inferred from the claim text.