Technique for high-speed TDF testing on low cost testers using on-chip or off-chip circuitry for RapidChip and ASIC devices
OwnerKevin Gearhardt, Richard Schultzinventors
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Abstract
TDF testing has become a requirement for any and all product applications for which product quality is of utmost concern, e.g. storage components. The specific problem with regard to TDF testing is that most production test systems cannot exceed a 200 Mhz effective TDF test rate. A higher speed solution for use with existing tester platforms is provided, without having to spend significant capital resources to upgrade to newer tester platforms. One solution adds circuitry to the test hardware used to interface to the DUT. Another solution adds circuitry to the actual design prior to releasing it for processing.
Claims13
A circuit configured to be interfaced with a clock pin of a device-under-test, said circuit configured to receive a plurality of clock pulses and provide the clock pulses in a stream to the clock pin of the device-under-test.
A circuit which is included on a device-under-test having a clock circuit, said circuit being interfaced with the clock circuit and configured to receive a clock pulse and a delayed version of the clock pulse and provide a clock pulse stream to the clock circuit.
Dependencies are inferred from the claim text.