Metacores: design and optimization techniques
AssigneeLSI Corporation
InventorsMiodrag Potkonjak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
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Abstract
A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.
Claims9
A decoder comprising:
- a memory storing a plurality state metrics implementing a decoder trellis;
- and
- a plurality of pointers each configured to store a branch in said decoder trellis spanning a plurality of time steps of said decoder trellis.
A decoder comprising:
- a memory storing a plurality state metrics implementing a decoder trellis;
- and
- a processor configured to (i) calculate a plurality of first branch metrics for a first half of a plurality of path segments in said decoder trellis in response to a signal received by said decoder, (ii) calculate a plurality of second branch metrics for a second half of said path segments based upon said first branch metrics and (iii) update said state metrics in response to said first branch metrics and said second branch metrics.
A decoder comprising:
- a memory storing a plurality state metrics implementing a decoder trellis;
- and
- a processor configured to (i) compute a plurality of branch metrics at each of a plurality of time steps of said decoder trellis substantially simultaneously and (ii) update said state metrics sequentially along said time steps based upon said branch metrics.
Dependencies are inferred from the claim text.