US 2006/0067433 A1 · Frequency-shift-keying demodulator and method of frequency-shift-keying

Abstract

The present invention relates to a frequency-shift-keying demodulator (1, 1′) comprising a phase shifter 2 for shifting the phase of an input signal i(t) by a predetermined degree and for outputting a shifted signal Id(t), a combining unit (3, 4; 31, 32, 33, 41, 42) for combining the input signal i(t) and the shifted signal Id(t) output by the phase shifter 2 and for outputting a corresponding signal r(t) and a low-pass filter 5 for filtering the signal r(t) output by the combining unit (3, 4; 31, 32, 33, 41, 42), and for outputting a low-pass filtered signal rLP(t) the bandwidth of said low-pass filter 5 being matched with the bandwidth of a data signal contained in said input signal i(t). According to the present invention said combining unit (3, 4; 31, 32, 33, 41, 42) comprises at least one adder (3; 31, 32) for adding the input signal i(t) and the shifted signal Id(t) output by the phase shifter 2 and for outputting an added signal and at least one square law detector (4; 41, 42) for receiving the added signal output by the adder (3; 31, 32) and for outputting a squared signal r(t) which is the square of the added signal wherein the combining unit (3, 4; 31, 32, 33, 41, 42) outputs the squared signal r(t) to the low-pass filter 5. Furthermore, the present invention relates to a method of frequency-shift-keying demodulating an input signal i(t).

Claims10

Dependent claims

A frequency-shift-keying demodulator (1, 1′) comprising

a phase shifter (2) for shifting the phase of an input signal (i(t)) by a predetermined degree and for outputting a shifted signal (Id(t));
a combining unit (3, 4;
31, 32, 33, 41, 42) for combining the input signal (i(t)) and the shifted signal (Id(t)) output by the phase shifter (2) and for outputting a corresponding signal (r(t));
and
a low-pass filter (5) for filtering the signal (r(t)) output by the combining unit (3, 4;
31, 32, 33, 41, 42), and for outputting a low-pass filtered signal (rLP(t)) the bandwidth of said low-pass filter (5) being matched with the bandwidth of a data signal contained in said input signal (i(t));
characterised in that
said combining unit (3, 4;
31, 32, 33, 41, 42) comprises
at least one adder (3;
31, 32) for adding the input signal (i(t)) and the shifted signal (Id(t)) output by the phase shifter (2) and for outputting an added signal;
and
at least one square law detector (4;
41, 42) for receiving the added signal output by the adder (3;
31, 32) and for outputting a squared signal (r(t)) which is the square of the added signal;
wherein the combining unit (3, 4;
31, 32, 33, 41, 42) outputs the squared signal (r(t)) to the low-pass filter (5).

14 more elements

Method of frequency-shift-keying demodulating an input signal (i(t)) comprising the steps of:

(S1) shifting the phase of an input signal (i(t)) by a predetermined degree and outputting a shifted signal (Id(t));
(S2, S3;
S21, S22, S23, S31, S32) combining the input signal (i(t)) and the shifted signal (Id(t)) and outputting a corresponding signal (r(t));
and
(S4) low-pass filtering the signal (r(t)) output by the combining step (S2, S3;
S21, S22, S23, S31, S32) and outputting a low-pass filtered signal (rLP(t));
characterised in that
the step (S2, S3;
S21, S22, S23, S31, S32) of combining the input signal (i(t)) and the shifted signal (Id(t)) and outputting a corresponding signal (r(t)) further comprises the steps of
(S2;
S21, S22) adding the input signal (i(t)) and the shifted signal (Id(t)) and outputting an added signal;
and
(S3;
S31, S32) generating and outputting a squared signal (r(t)) which is the square of the added signal;
wherein said squared signal (r(t)) is filtered in the step (S4) of low-pass filtering the signal output by the combining step (S2, S3;
S21, S22, S23, S31, S32).

13 more elements

Dependencies are inferred from the claim text.

Frequency-shift-keying demodulator and method of frequency-shift-keying

Life of this patent

Frequency-shift-keying demodulator and method of frequency-shift-keying

Life of this patent

Abstract

Claims10