Method and apparatus for SDH/SONET frame alignment
AssigneeHuawei Technologies Co., Ltd.
InventorFengguo Yang
Life of this patent
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Abstract
The invention discloses a frame alignment method. Based on time-sharing structure of SDH/SONET data, the methods use one common circuit to complete functions like pointer interpretation, pointer generation and payload interception and storage, etc. The method stores information of every channel which is being processed respectively, and then controls reading and writing memories and the operations of the whole common circuit by the scheduling of input signals. The invention also opens a frame aligning circuit; improves circuit efficiency by multiplexing common circuit while decreases logistic scale of processing. The invention is mainly engaged to frame alignment of a SDH/SONET system.
Claims12
A frame aligning method, comprises the steps of:
- processing every channel of a frame time-sharingly through common circuits including at least a common pointer interpreter module and a pointer generator module;
- based on the structure and control information of the frame to be aligned, said common circuit generating the receiving pulses indicating positions of a channel pointer's first byte and second byte;
- said common pointer interpreter module receiving the first-byte and second-byte information of all channel pointers according to said receiving pulses, and storing the first-byte information;
- according to the channel sequence, said common pointer interpreter module interpreting channel pointers to obtain pointer status information;
- according to the state information obtained, the common pointer interpreter module generating control signals to store channel payload;
- generating a time signal for a new frame required and providing to said pointer generator module;
- based on pointer offset and adjustment information of each channel, said pointer generator module creating new channel pointers for all channels;
- generating the control signal according to timing signals of said new frame and the new channel pointers generated by said pointer generator;
- with said control signal, reading the payload and generated pointer of each channel to form aligned data frame.
A frame aligning integrated circuit comprising a receiving timer, a pointer interpreter module, a transmitting timer, a pointer generator module and a first memory;
- wherein said receiving timer is connected with the pointer interpreter module and the first memory respectively receives frame to be aligned and the frame control signals, and then based on the frame control signals, it generates timing signals indicating different positions of frame signals;
- and sends the timing signals to pointer interpreter module;
- based on timing signals and pointer interpretation results given by pointer interpreter module, it controls the first memory to store frame data;
- and
- wherein said pointer interpreter module is connected with the receiving timer, and receives frame to be aligned;
- under control by timing signals from the receiving timer, interprets channel pointers of Tributary Units in a frame;
- sends pointer interpretation results to the receiving timer;
- and,
- wherein said transmitting timer is connected with the pointer generator module and first memory, receives control signals for new frame system requires;
- based on the frame control signals, it generates timing signals indicating different positions of a new frame, based on timing signals and new channel pointer state sent by pointer generator module, controls the first memory to read frame data;
- and,
- wherein said pointer generator module is connected with the transmitting timer and first memory;
- under control of timing signals provided by the transmitting timer, creates new channel pointers of Tributary Units and stores the new channel pointers into the first memory;
- and,
- wherein said first memory is connected with the receiving timer, transmitting timer and pointer generator module, stores payloads of all channels under the control of timing signals provided by the receiving timer;
- and stores newly generated pointers of all channels, and outputs payloads and new pointers of all channels under the control of timing signals provided by the transmitting timer.
Dependencies are inferred from the claim text.