Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length
AssigneeSamsung Electronics Co., Ltd.
InventorOne-gyun La
Life of this patent
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Abstract
The present invention provides a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. The DDR integrated circuit memory device is further configured to support a sequential address increase scheme and an interleave address increase scheme.
Claims16
An integrated circuit memory device using a 4 bit prefetch scheme, the integrated circuit memory device comprising:
- a serial/parallel converter which converts sequentially input serial data of 4 bits each into parallel data;
- a parallel/serial converter which converts parallel data that will be output into serial data;
- and
- a column decoder which generates first through eighth pre-decoding signals using 3 bits of a plurality of bits constituting a column address to activate column select lines that designate columns where the 8 parallel data will be input to or output from,
- wherein the column decoder activates at the same time column select lines that belong to a first group and designate columns where the first parallel converted 4 data of the 8 parallel data will be input to or output from, using the first through eighth pre-decoding signals for a first cycle, and activates at the same time column select lines that belong to a second group and designate columns where the other 4 data of the 8 parallel data will be input to or output from, using inverted signals of the first through eighth pre-decoding signals for the second cycle.
An integrated circuit memory device using a 2 bit prefetch scheme, the integrated circuit memory device comprising:
- a serial/parallel converter which converts sequentially input serial data of 2 bits each into parallel data;
- a parallel/serial converter which converts parallel data that will be output into serial data;
- and
- a column decoder which generates 4 pre-decoding signals using 2 bits of a plurality of bits constituting the column address to activate column select lines that designate columns where 4 parallel data will be input to or output from,
- wherein the column decoder activates column select lines that belong to a first group and designate columns where first parallel converted 2 data of the 4 parallel data will be input to or output from at the same time for the first cycle using the 4 pre-decoding signals, and activates column select lines that belong to a second group and designate columns where the other 2 data of the 4 parallel data will be input to or output from at the same time for the second cycle using inverted signals of the 4 pre-decoding signals.
An integrated circuit memory device using an N (N is a natural number of 2 or more), bit prefetch scheme and a 2N burst length, the integrated circuit memory device comprising:
- a serial/parallel converter which converts sequentially input 2N data of N bits each into parallel data;
- a parallel/serial converter which converts data that will be output into serial data;
- and
- a column decoder for generating 2N pre-decoding signals using a predetermined number of bits of a plurality of bits constituting a column address to activate column select lines that designate columns where the 2N parallel data will be input to or output from,
- wherein the column decoder activates column select lines that belong to a first group and designate columns where the first parallel converted N data of the 2N parallel data will be input to or output from at the same time using the 2N pre-decoding signals for a first cycle, and activates column select lines that belong to a second group and designate columns where the other N data of the 2N parallel data will be input to or output from at the same time using inverted signals of the 2N pre-decoding signals for a second cycle.
Dependencies are inferred from the claim text.