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US 2006/0067155 A1Published application
Latency normalization by balancing early and late clocks
AssigneeIntel Corporation
InventorsHing To, Joe Salmon, Mamun Rashid
Life of this patent
Estimating the term…
Abstract
A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal.
Claims31
A method, comprising:
- a first memory device and a second memory device receiving an early clock signal;
- the first memory device and the second memory device receiving a late clock signal;
- and
- the first memory device and the second memory device generating average clock signals by averaging the early clock signal and the late clock signal, wherein the first memory device's average clock signal and the second memory device's average clock signal are synchronous.
1 more element
An apparatus, comprising:
- a clock signal trace;
- and
- a memory device, the memory device operable to:
- receive an early clock signal from the clock signal trace and a late clock signal from the clock signal trace;
- and
- generate an average clock signal by averaging the early clock signal and the late clock signal.
3 more elements
A method, comprising:
- a memory device receiving an early clock signal and a late clock signal;
- and
- the memory device generating an average clock signal by averaging the early clock signal and the late clock signal.
A system, comprising:
- a clock signal trace;
- a chipset coupled to the clock signal trace;
- and
- a memory device coupled to the clock signal trace, the memory device operable to:
- receive an early clock signal from the clock signal trace and a late clock signal from the clock signal trace;
- and
- generate an average clock signal by averaging the early clock signal and the late clock signal.
4 more elements
Dependencies are inferred from the claim text.