Memory arrangement
AssigneeInfineon Technologies AG
InventorsDietmar Scheiblhofer, Jurgen Jernej
Life of this patent
Estimating the term…
Abstract
A memory arrangement including a memory array, which has at least one memory block with a power supply device which can be activated, an address decoder, which is coupled to the at least one memory block in order to control access to the at least one memory block, and an activation device for selectively activating the power supply device of memory blocks. The address decoder is set up to interact with the activation device in such a manner that, when a memory block is accessed for the first time, the power supply device of the memory block is activated and remains activated after the access operation has ended.
Claims13
A memory arrangement comprising:
- a memory array, which comprises at least one memory block having a power supply device which can be activated;
- an address decoder, which is coupled to the at least one memory block in order to control access to the at least one memory block;
- and
- an activation device for selectively activating the power supply device of memory blocks,
- wherein the address decoder is set up to interact with the activation device in such a manner that, when a memory block is accessed for the first time, the power supply device of said memory block is activated and remains activated after the access operation has ended.
A method for operating a memory arrangement, comprising the steps of:
- putting at least one memory block of a memory array into an active operating state, when accessed, by activating a power supply for the memory block;
- and
- having the at least one memory block remain in the active operating state.
A memory arrangement comprising:
- a memory array, which comprises at least one memory block having a power supply device which can be activated;
- an address decoder, which is coupled to the at least one memory block in order to control access to the at least one memory block;
- and
- an activation means for selectively activating the power supply device of memory blocks,
- wherein the address decoder is set up to interact with the activation means in such a manner that, when a memory block is accessed for the first time, the power supply device of said memory block is activated and remains activated after the access operation has ended.
Dependencies are inferred from the claim text.