Memory
AssigneeSanyo Electric Co., Ltd.
InventorHideaki Miyamoto
Life of this patent
Estimating the term…
Abstract
A memory capable of performing a refresh operation without increasing current consumption is provided. This memory comprises a plurality of memory cells storing data, a delay circuit outputting a first address signal corresponding to the memory cells received from outside for a normal access operation with a delay of a prescribed period, a refresh control circuit outputting a second address signal corresponding to any of the memory cells subjected to a refresh operation of the data and a switching circuit switching and outputting the first address signal output from the delay circuit and the second address signal output from the refresh control circuit.
Claims20
A memory comprising:
- a plurality of memory cells storing data;
- a delay circuit outputting a first address signal corresponding to said memory cells received from outside for a normal access operation with a delay of a prescribed period;
- a refresh control circuit outputting a second address signal corresponding to any of said memory cells subjected to a refresh operation of said data;
- and
- a switching circuit switching and outputting said first address signal output from said delay circuit and said second address signal output from said refresh control circuit.
A memory comprising:
- a plurality of word lines and a plurality of bit lines arranged to intersect with each other;
- a plurality of memory cells arranged on positions corresponding to the intersections between said plurality of word lines and said plurality of bit lines respectively and including ferroelectric capacitors connected to corresponding said word lines and corresponding said bit lines for storing data;
- a delay circuit outputting a first address signal corresponding to said memory cells received from outside for a normal access operation with a delay of a prescribed period;
- a refresh control circuit outputting a second address signal corresponding to any of said memory cells subjected to a refresh operation of said data;
- and
- a switching circuit switching and outputting said first address signal output from said delay circuit and said second address signal output from said refresh control circuit.
Dependencies are inferred from the claim text.