Arrangement and method for reading from resistance memory cells
AssigneeInfineon Technologies AG
InventorThomas Roehr
Life of this patent
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Abstract
A method and apparatus for reading from a memory arrangement, in particular, for reading from a CBRAM or another memory arrangement based on resistively switching memory cells includes charging a bit line to a voltage value, discharging the bit line by a cell resistance, and subsequently assessing a resulting voltage difference in a measuring device, in particular, a differential sense amplifier.
Claims33
A method for reading from a memory arrangement including at least one memory cell in which a resistance value between two poles of the memory cell reflects a memory state of the memory cell, the method comprising:
- connecting one of the two poles to a charge source with a first potential;
- connecting the other of the two poles to a conductor having a second potential, which lies below the potential of the charge source;
- and
- measuring the potential of the conductor.
A method for reading from a memory arrangement including at least one memory cell in which a resistance value between two poles of the memory cell reflects a memory state of the memory cell, the method comprising:
- connecting one of the two poles to a charge sink with a first potential;
- connecting the other of the two poles to a conductor having a second potential, which lies above the potential of the charge sink;
- and
- measuring the potential of the conductor.
An apparatus for reading from a memory arrangement including at least one memory cell in which a resistance value between two poles of the memory cell reflects a memory state of the memory cell, the apparatus comprising:
- a charge source with a first potential for connecting to one of the two poles;
- a conductor having a second potential, which lies below the potential of the charge source, for connecting to the other of the two poles;
- and
- a measuring device for measuring the potential of the conductor.
An apparatus for reading from a memory arrangement including at least one memory cell in which a resistance value between two poles of the memory cell reflects a memory state of the memory cell, the apparatus comprising:
- a charge sink with a first potential for connecting to one of the two poles;
- a conductor having a second potential, which lies above the potential of the charge sink, for connecting to the other of the two poles;
- and
- a measuring device for measuring the potential of the conductor.
Dependencies are inferred from the claim text.