Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device

A method for controlling a shift redundancy circuit that selectively connects a plurality of selection lines and at least one redundancy selection line, each of which commonly shares a plurality of memory blocks, to a plurality of decode selection lines, and remedies a deficiency relating to each of the plurality of selection lines for each memory block, the method comprising the steps of:

• generating a decode signal by decoding a deficiency address indicating a deficient location in response to a set signal;
• generating and holding, individually for each memory block having a deficiency to be remedied, a shift signal for determining the plurality of decode selection lines that are to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on the decode signal;
• selecting a held shift signal that corresponds to a selected memory block having a deficiency to be remedied, based on a memory block selection signal;
• and
• selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the selected shift signal.

A shift redundancy circuit for selectively connecting a plurality of selection lines and at least one redundancy selection line, each of which commonly shares a plurality of memory blocks, to a plurality of decode selection lines, and remedying a deficiency relating to each of the plurality of selection lines for each memory block, the circuit comprising:

• a shift control circuit for generating a shift signal for determining the plurality of decode selection lines to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on a deficiency address indicating a deficient location and a redundancy selection signal for selecting the redundancy selection line;
• a shift information selection circuit, connected to the shift control circuit, for outputting a shift signal selected by the shift control circuit, based on a set signal, for each memory block having a deficiency to be remedied;
• a shift information latch circuit, connected to the shift information selection circuit, for latching a shift signal output from the shift information selection circuit;
• a shift signal selection circuit, connected to the information latch circuit, for selecting a shift signal corresponding to a selected memory block having a deficiency to be remedied and latched by the shift information latch circuit, based on a memory block selection signal;
• and
• a switch circuit, connected to the shift signal selection circuit, for selectively connecting a plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the shift signal selected by the shift signal selection circuit.

A semiconductor memory device comprising:

• a plurality of memory blocks;
• a plurality of selection lines and at least one redundancy selection line, each of which commonly shares the plurality of memory blocks;
• a plurality of decode selection lines;
• and
• a shift redundancy circuit for selectively connecting the plurality of selection lines and the at least one redundancy selection line to the plurality of decode selection lines, and remedying a deficiency relating to each of the plurality of selection lines for each memory block, wherein the shift redundancy circuit includes:
• a shift control circuit for generating a shift signal for determining and controlling switching of connection destinations of the plurality of decode selection lines to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on a deficiency address indicating a deficient location and a redundancy selection signal for selecting the redundancy selection line;
• a shift information selection circuit, connected to the shift control circuit, for outputting a selected shift signal that is generated by the shift control circuit based on a set signal for each memory block having a deficiency to be remedied;
• a shift information latch circuit, connected to the shift information selection circuit, for latching a shift signal output from the shift information selection circuit;
• a shift signal selection circuit, connected to the information latch circuit, for selecting, when a memory block having a deficiency to be remedied is selected, a shift signal that corresponds to the selected memory block and that is latched in advance by the shift information latch circuit, based on a memory block selection signal;
• and
• a switch circuit, connected to the shift signal selection circuit, for changing a connection destination of at least one of the plurality of decode selection lines, and selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line so that the connection destinations of the plurality of decode selection lines are shifted based on the shift signal selected by the shift signal selection circuit.