Integrated circuit buffer device
AssigneeRambus Inc.
InventorsRichard Perego, Stefanos Sidiropoulos, Ely Tsern
Life of this patent
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Abstract
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link
Claims56
1-24. (canceled)
An integrated circuit master device comprising:
- a first point-to-point link port to communicate with a buffer device of a first memory subsystem;
- and
- a second point-to-point link port to communicate with a buffer device of a second memory subsystem;
- and
- termination coupled to the first point-to-point link port.
(canceled)
An integrated circuit device comprising:
- a point-to-point link port to communicate data to a buffer device of a memory subsystem, the point-to-point link port including transmitter circuitry to output the data such that the data is synchronous with respect to a first clock signal and travels alongside the first clock signal;
- and
- termination coupled to the point-to-point link port.
An integrated circuit controller device comprising:
- a first point-to-point link port to communicate data with a buffer device of a first memory subsystem, the first point-to-point link port including:
- transmitter circuitry to output a first differential data signal that includes encoded clock information;
- receiver circuitry to receive a second differential data signal that includes encoded clock information;
- and
- termination coupled to the transmitter and receiver circuitry.
An integrated circuit processor device that communicates data with a buffered memory subsystem via a point-to-point link, the integrated circuit processor device comprising:
- transmitter circuitry to output data to the buffer device via a first external unidirectional signal line of the point-to-point link;
- receiver circuitry to receive data from the buffer device via a second external unidirectional signal line of the point-to-point link;
- first termination coupled to the first external unidirectional signal line;
- and
- second termination coupled to the second external unidirectional signal line.
(canceled)
An integrated circuit processor device comprising a first point-to-point link port to communicate with a first buffered memory subsystem, wherein the first point-to-point link port comprises:
- transmitter circuitry to transmit differential transmit signals to a first pair of external unidirectional point-to-point link endpoints, wherein the differential transmit signals are clocked synchronously with respect to a first clock signal, wherein the differential signals travel alongside the first clock signal;
- receiver circuitry to receive differential receive signals from a second pair of external unidirectional point-to-point link endpoints, wherein the differential receive signals are clocked synchronously with respect to a second clock signal, wherein the differential signals travel alongside the second clock signal;
- first termination coupled to the first pair of external unidirectional point-to-point link endpoints;
- and
- second termination coupled to the second pair of unidirectional point-to-point link endpoints.
An integrated circuit master device comprising:
- a first point-to-point link interface means for communicating data with a buffer device of a first memory subsystem;
- first termination means for terminating the first point-to-point link means;
- a second point-to-point link interface means for communicating data with a buffer device of a second memory subsystem;
- and
- second termination means for terminating the second point-to-point link means.
An integrated circuit master device comprising:
- a first point-to-point link port to communicate with a buffer device of a first memory subsystem,
- wherein the first point-to-point link port is configured to communicate using differential signaling;
- and
- a second point-to-point link port to communicate with a buffer device of a second memory subsystem.
An integrated circuit device that communicates data with a buffer device of a buffered memory subsystem via a point-to-point link, the integrated circuit device comprising:
- transmitter circuitry to output data to the buffer device via a first external unidirectional signal line of the point-to-point link;
- receiver circuitry to receive data from the buffer device via a second external unidirectional signal line of the point-to-point link;
- and
- an interface to communicate sideband signals that include initialization instructions to the buffered memory subsystem.
Dependencies are inferred from the claim text.