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US 2006/0067136 A1Published application
Low leakage and leakage tolerant stack free multi-ported register file
AssigneeIntel Corporation
InventorsSteven Hsu, Amit Agarwal, Ram Krishnamurthy
Life of this patent
Estimating the term…
Abstract
A device includes a number of memory cells. Each of the memory cells includes a transistor stack coupled to a bit line. A value of a charge on the bit line during an access mode represents a value of data stored in an accessed memory cell. During a non-access mode, all transistors of the transistor stack are turned off to save power. The transistors are turn off regardless of the value of the data stored in the memory cells.
Claims30
A device comprising:
- a bit line;
- a transistor stack coupled between the bit line and a supply node;
- a memory unit;
- and
- an isolation unit to isolate the transistor stack from the memory unit.
2 more elements
A device comprising:
- a plurality of bit lines;
- a plurality of select lines;
- a plurality of first memory cells, each of the first memory cells coupled to a first bit line of the plurality of bit lines;
- and
- a plurality of second memory cells, each of the second memory cells coupled to a second bit line of the plurality of the bit lines, wherein each memory cell of the first memory cells and the second memory cells includes a transistor stack coupled between one of the bit lines and a supply node, a memory unit, and an isolation unit coupled between the transistor stack and the memory unit.
2 more elements
A system comprising:
- a processing unit;
- and
- a cache memory device coupled to the processing unit, at least one of the processing unit and the cache memory device including a register file, the register file including:
- a bit line;
- a transistor stack coupled between the bit line and a supply node;
- a memory unit to store complementary bit values of a data bit;
- and
- an isolation unit coupled between the transistor stack and the memory unit.
5 more elements
A method comprising:
- holding a bit line at a first value when a select line coupled to a memory cell is activated and a memory unit of a memory cell has a first bit value;
- creating a conductive path between the bit line and a supply node to change the first value of the bit line to a second value when the select line is activated and the memory unit of the memory cell has a second bit value, wherein the conductive path runs through a transistor stack of the memory cell;
- and isolating the transistor stack from the memory unit of the memory cell when the select line is deactivated.
Dependencies are inferred from the claim text.