Method for reading electrically programmable and erasable memory cells, with bit line precharge-ahead
AssigneeSTMicroelectronics S.r.l.
InventorsFrancesco La Rosa, Thierry Giovinazzi
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Abstract
The present invention relates to a method for reading memory cells by means of sense amplifiers, the memory cells being linked to bit lines, the reading of each memory cell comprising a phase of precharging the bit line to which the memory cell is linked and a phase of actually reading the memory cell. According to the present invention, each sense amplifier is used to precharge at least two bit lines, then to read one memory cell in one of the precharged bit lines. The present invention applies particularly to serial memories, for the precharge-ahead of bit lines having the same partial address, while a read address is being received.
Claims20
A method for reading memory cells by means of sense amplifiers, the memory cells being linked to bit lines, the reading of each memory cell comprising a phase of precharging the bit line to which the memory cell is linked and a phase of actually reading the memory cell, a method characterised in that each sense amplifier is used to precharge at least two bit lines, then to read one and only one memory cell on one of the precharged bit lines.
A memory comprising memory cells linked to bit lines, sense amplifiers and a column decoder linking each sense amplifier to a group of bit lines, wherein the reading of memory cells comprises a phase of precharging, by the sense amplifiers, the bit lines to which the memory cells to be read are linked, and a phase of actually reading the memory cells by the sense amplifiers,
- characterized in that it comprises means for forcing the decoder, during the precharge phase, to link each sense amplifier to at least two bit lines of a same column, then, during the reading phase, releasing the decoder so that it links each sense amplifier to one and only one bit line of the column.
A method for reading a memory cell, comprising:
- obtaining a portion of a complete memory address, the portion addressing a plurality of memory cells;
- simultaneously precharging a plurality of bit lines, wherein each bit line is coupled to one of the memory cells;
- obtaining the complete memory address;
- selecting one of the bit lines based on the complete memory address;
- and
- reading the memory cell coupled to the selected bit line.
An apparatus for reading a memory cell, comprising:
- a plurality of bit lines, wherein each bit line is coupled to one of a plurality of memory cells addressed by a portion of a complete memory address;
- a charge circuit configured to simultaneously precharge the bit lines;
- a decoder configured to select one of the bit lines based on the complete memory address;
- and
- a sense amplifier configured to read the memory cell coupled to the selected bit line.
Dependencies are inferred from the claim text.