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US 2006/0067128 A1Published application
Flash memory
AssigneeMicron Technology, Inc.
InventorsAndrei Mihnea, Chun Chen
Life of this patent
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Abstract
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.
Claims21
A flash memory, comprising:
- at least one floating-gate memory cell comprising a source, a drain, a control gate, a floating gate and a substrate;
- a memory control circuit for controlling operations on the at least one floating-gate memory cell;
- a wordline coupled to the control gate of the at least one memory cell;
- and
- a wordline drive transistor coupled to the wordline;
- wherein the memory control circuit is adapted to apply a negative voltage to the control gate relative a common voltage while applying a positive voltage to the source relative the common voltage;
- wherein the memory control circuit is further adapted to begin discharging the positive voltage at a rate sufficient to increase a magnitude of the negative voltage applied to the control gate;
- and
- wherein the memory control circuit is further adapted to begin discharging the negative voltage after an increase in the magnitude of the negative voltage has occurred.
6 more elements
A flash memory, comprising:
- at least one floating-gate memory cell comprising a source, a drain, a control gate, a floating gate and a substrate;
- a memory control circuit for controlling operations on the at least one floating-gate memory cell;
- a wordline coupled to the control gate of the at least one memory cell;
- and
- a wordline drive transistor coupled to the wordline and having a parasitic drain capacitance on the order of 1-10 fF;
- wherein the memory control circuit is adapted to apply a negative voltage to the control gate relative a common voltage while applying a positive voltage to the source relative the common voltage;
- wherein the memory control circuit is further adapted to begin discharging the positive voltage at a rate sufficient to increase a magnitude of the negative voltage applied to the control gate by at least 3V;
- and
- wherein the memory control circuit is further adapted to begin discharging the negative voltage after an increase in the magnitude of the negative voltage has occurred.
6 more elements
A flash memory, comprising:
- at least one floating-gate memory cell comprising a source, a drain, a control gate, a floating gate and a substrate;
- a memory control circuit for controlling operations on the at least one floating-gate memory cell;
- a wordline coupled to the control gate of the at least one memory cell;
- and
- a wordline drive transistor coupled to the wordline;
- wherein the memory control circuit is adapted to apply a negative voltage to the control gate relative a common voltage while applying a positive voltage to the source relative the common voltage;
- wherein the memory control circuit is further adapted to begin discharging the positive voltage at a rate sufficient to increase a magnitude of the negative voltage applied to the control gate by at least 3V;
- wherein the rate of discharging the positive voltage is a rate sufficient to discharge the positive voltage in a fraction of 1 ms;
- and
- wherein the memory control circuit is further adapted to begin discharging the negative voltage after an increase in the magnitude of the negative voltage has occurred.
7 more elements
Dependencies are inferred from the claim text.