SRAM cell with horizontal merged devices

An apparatus comprising:

• means for applying a potential difference (VDIFF) to each of a plurality of memory cells by providing a column potential (VC) on a column line and a row potential (VR) on a row line;
• means for resetting a first selected memory cell to a zero state by decreasing VDIFF by an increment more than a transistor threshold voltage (VT) to reset the selected memory cell to a zero state;
• means for writing a second selected memory cell to a one state by increasing VDIFF by an increment more than VT to set the selected memory cell to the one state;
• and
• means for reading a third selected memory cell including:
• means for increasing VDIFF by an increment less than VT;
• and
• means for determining whether the increased VDIFF results in a current flow on the column line for the selected memory cell.

An apparatus, comprising:

• means for reading a selected memory cell, including:
• means for applying a first potential difference (VDIFF) to the selected memory cell, including means for providing a column potential (VC) on a column line and a row potential (VR) on a row line;
• means for increasing VDIFF by an increment less than a transistor threshold voltage (VT);
• and
• means for determining whether the increased VDIFF results in a current flow on the column line for the selected memory cell;
• and
• means for writing the selected memory cell, including:
• means for applying a second potential difference (VDIFF) to the selected memory cell, including means for providing a column potential (VC) on a column line and a row potential (VR) on a row line;
• and
• means for increasing VDIFF by an increment more than a transistor threshold voltage (VT) to set the selected memory cell to a one state.