Phase-tolerant pixel rendering of high-resolution analog video

A circuit that generates a sequence of digital values for a corresponding sequence of analog voltages in each analog signal of an analog input, the analog voltages in each analog signal occurring at an identical fixed rate with a corresponding fixed time-period for each analog voltage level, the analog input comprising a minimum of one analog signal, the circuit comprising:

• a phase-locked-loop that generates a clock signal synchronized to the analog input with a frequency that is an integer multiple of the rate of the analog voltage levels in each analog signal so that an integer number of clock cycles occur over the time-period of each input voltage level, said integer number of clock cycles comprising a sequence of clock phases that is repeated for the time-period of each input voltage level;
• a sampling analog-to-digital converter for each analog signal that generates a digital sample of the analog signal at each cycle of the clock signal;
• a rendering circuit for each analog signal that determines each digital value in the sequence of digital values from at least one sample in a group of samples from the analog-to-digital converter that occur within a time-window that brackets a selected nominal phase of the clock signal;
• and
• a local phase adjustment means for each analog signal for selecting the at least one sample wherein the local phase adjustment means locates possible transitions in the voltage level by determining difference values between samples from the analog-to-digital converter that are in close proximity and comparing the relative magnitudes of the difference values and wherein the selection of the at least one sample excludes samples that may be near transitions in the voltage level of the analog signal.

A method for generating a sequence of digital values for a corresponding sequence of analog voltages in each analog signal of an analog input, the analog voltages in each analog signal occurring at an identical fixed rate with a corresponding fixed time-period for each analog voltage level, the analog input comprising a minimum of one analog signal, the method comprising the steps of:

• generating a clock signal synchronized to the analog input with a frequency that is an integer multiple of the rate of the analog voltage levels in each analog signal so that an integer number of clock cycles occur over the time-period of each input voltage level, said integer number of clock cycles comprising a sequence of clock phases that is repeated for the time-period of each input voltage level;
• generating a digital sample for each analog signal at each cycle of the clock signal;
• locating possible transitions in the voltage level for each analog signal by determining difference values between samples that are in close proximity and comparing the relative magnitudes of the difference values;
• and
• determining each digital value in the sequence of digital values for each analog signal from at least one sample in a group of samples that occur within a time-window that brackets a selected nominal phase of the clock signal wherein the at least one sample excludes samples that may be near transitions in the voltage level of the analog signal.

A circuit that generates a sequence of digital values for a corresponding sequence of analog voltages in each analog signal of an analog input, the analog voltages in each analog signal occurring at an identical fixed rate with a corresponding fixed time-period for each analog voltage level, the analog input comprising a minimum of one analog signal, the circuit comprising:

• a phase-locked-loop that generates a clock signal synchronized to the analog input with a frequency that is an integer multiple of the rate of the analog voltage levels in each analog signal so that an integer number of clock cycles occur over the time-period of each input voltage level, said integer number of clock cycles comprising a sequence of clock phases that is repeated for the time-period of each input voltage level;
• a sampling analog-to-digital converter for each analog signal that generates a digital sample of the analog signal at each cycle of the clock signal;
• a rendering circuit for each analog signal that determines each digital value in the sequence of digital values from at least one sample in a group of samples from the analog-to-digital converter that occur within a time-window that brackets a selected nominal phase of the clock signal;
• a global phase detection means for locating transitions in the voltage levels of at least one analog signal of the analog input in order to determine an optimum clock phase for each analog signal;
• and
• a global phase adjustment means for selecting the optimum clock phase of each analog signal, as determined by the global phase detection means, to be the nominal clock phase for the rendering circuit of the analog signal.

A method for generating a sequence of digital values for a corresponding sequence of analog voltages in each analog signal of an analog input, the analog voltages in each analog signal occurring at an identical fixed rate with a corresponding fixed time-period for each analog voltage level, the analog input comprising a minimum of one analog signal, the method comprising the steps of:

• generating a clock signal synchronized to the analog input with a frequency that is an integer multiple of the rate of the analog voltage levels in each analog signal so that an integer number of clock cycles occur over the time-period of each input voltage level, said integer number of clock cycles comprising a sequence of clock phases that is repeated for the time-period of each input voltage level;
• generating a digital sample for each analog signal at each cycle of the clock signal;
• locating transitions in the voltage levels of at least one analog signal of the analog input in order to determine an optimum clock phase for each analog signal;
• and
• determining each digital value in the sequence of digital values for each analog signal from at least one sample in a group of samples that occur within a time-window that brackets the optimum phase of the clock signal.