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OwnerDipankar Bhattacharya, John Kriz +3inventors
InventorsDipankar Bhattacharya, John Kriz, Brian Lacey, Bruce McNeill, Bernard Morris
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A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal and a latch circuit for storing a signal at an output of the latch circuit which is representative of a logical state of the input signal. The latch circuit includes an input coupled to the input stage. The voltage level translator circuit further includes a feedback circuit coupled between the input and the output of the latch circuit. The feedback circuit is operative to maintain a desired logic state of the voltage level translator circuit when the second voltage supply powers up before the first voltage supply. In this manner, the voltage level translator circuit is configured to provide an output signal having a predictable logic state over a wide variation of PVT conditions and/or voltage supply ramp rates.
A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the circuit comprising:
An integrated circuit including at least one voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the at least one voltage level translator circuit comprising:
Dependencies are inferred from the claim text.