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US 2006/0066375 A1Published application
Delay line synchronizer apparatus and method
AssigneeMicron Technology, Inc.
InventorPaul LaBerge
Life of this patent
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Abstract
A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.
Claims2
A method for generating a clock signal, comprising:
- receiving a first clock signal;
- generating a second clock signal based on the first clock signal, the second clock signal having a higher clock frequency than the first clock signal and further having a phase relationship with respect to the first clock signal related to a first time delay and relative to a rising or falling edge of the first clock signal;
- adjusting the first time delay to which the phase relationship between the first and second clock signals is related to a second time delay;
- monitoring the phase relationship between the first and second clock signals during adjustment of the first time delay to the second time delay;
- and
- generating a third clock signal based on the first clock signal, the third clock signal having the clock frequency of the second clock signal and having a phase relationship with respect to the first clock signal related to the second time delay relative to the rising or falling edge to which the first time delay was relative.
3 more elements
2-55. (canceled)
Dependencies are inferred from the claim text.