Switched operation amplifier

A switched operation amplifier comprising:

• a biased circuit, providing a first, a second, and a third biased signal;
• a amplifier circuit, having a first transistor, a second differential pair, a third, a fourth, a fifth current mirror, a sample-and-hold switch, and a complementary sample-and-hold switch, wherein said first transistor is controlled by said first biased signal so as to provide two reference currents for said third, and fourth current mirror, which are, respectively, connected with two transistors of said second differential pair, further, a mirror current of said third current mirror being controlled by said third biased signal to determine whether said third mirror current of said third current mirror is fed into a reference terminal of said fifth current mirror or not, and still a mirror current terminal of said fourth current mirror being connected with both of said sample-and-hold switch and said complementary sample-and-hold switch so as to provide a current path either though said sample-and-hold switch to a mirror terminal of said fifth current mirror, or said complementary sample-and-hold switch to ground depending on sampling mode or holding mode being selected, still two gates of said two transistors of said second differential pair served, respectively, as a positive and a negative terminal;
• and
• a buffer circuit having a capacitor, a second and a third transistor wherein said capacitor connected between ground and a node connected both of said sample-and-hold switch and a gate of said second transistor, and still a source terminal of said second transistor connected with a drain terminal of said third transistor, furthermore, said source terminal of said second transistor is served as a signal output terminal and fed back to said negative terminal and said third transistor is controlled by said second biased signal.