Latch clock generation circuit and serial-parallel conversion circuit

A latch clock generation circuit comprising a plurality of latch signal generation circuits which receive a system clock signal changing based on a predetermined period and output a latch signal with a period of an integer multiple of the predetermined period of the system clock signal, the plurality of latch signal generation circuits being connected to each other in series, wherein the latch signal generation circuit includes:

• a gate circuit which receives a control signal and a feedback signal, and outputs according to a combination of the received control signal and the feedback signal, a latch signal obtained by inverting a pulse corresponding to one clock of the system clock signal;
• and
• an output synchronization circuit which holds the latch signal output from the gate circuit and outputs the latch signal as a control signal supplied to a gate circuit of the latch signal generation circuit of the succeeding stage and the feedback signal supplied to the gate circuit of the self stage.