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US 2006/0066355 A1Published application
Voltage tolerant structure for I/O cells
AssigneeAtmel Corporation
InventorsVincent Gosmain, David Bernard
Life of this patent
Estimating the term…
Abstract
An input/output (I/O) buffer having an input mode and coupled between first and second supply voltages includes a PMOS pull-up transistor fabricated in an nwell, and a gate bias control transistor coupled to the gate of the PMOS pull-up transistor for coupling the gate of the PMOS pull-up transistor to an input/output node in response to an input signal having a voltage greater than approximately the first supply voltage. A well bias control circuit is coupled to the PMOS pull-up transistor and to a well drive transistor to couple the nwell terminal to the first supply voltage in response to the input signal having a voltage approximately equal to or less than the first supply voltage.
Claims26
A method of preventing conduction in a PMOS pull-up transistor in an input/output buffer having an input node and operating in an input mode, when the input node is subjected to a voltage exceeding a first power supply voltage to the buffer, the method comprising:
- fabricating the PMOS pull-up transistor in an nwell;
- coupling the gate terminal of the PMOS pull-up transistor to the input node by a second PMOS transistor;
- raising the potential of the nwell by means of conduction through a pn source to bulk diode of at least one PMOS device such that the nwell potential approximately equals the input node voltage;
- and
- providing pull-down means to a gate terminal of a well drive transistor coupling the first power supply voltage to the nwell by a third PMOS transistor.
2 more elements
An apparatus having an input mode and coupled between first and second supply potentials, the apparatus comprising:
- an input/output node to receive an input signal;
- a PMOS pull-up transistor having gate, source, drain and body terminals, and fabricated in an nwell, the source terminal coupled to the first supply potential and the drain terminal coupled to the input/output node;
- an NMOS pull-down transistor having source and drain terminals, the source terminal coupled to the second supply potential and the drain terminal coupled to the input/output node;
- a gate bias control transistor having gate, source, and drain terminals, the source terminal coupled to the input node, the drain coupled to the gate of the PMOS pull-up transistor, and the gate terminal coupled to the first supply potential and configured to couple the gate of the PMOS pull-up transistor to the input/output node in response to the input signal having a potential greater than approximately the first supply potential;
- a passgate having an NMOS passgate transistor and a PMOS passgate transistor, the NMOS passgate transistor and the PMOS passgate transistor each having source and drain terminals, the source terminals of each passgate transistor coupled to each other and to a circuit node with a potential configured to be approximately equal to the first supply potential during the input mode, and the drain terminals coupled to each other and to the gate of the PMOS pull-up transistor and configured to couple the gate of the PMOS pull-up transistor to the first supply potential in response to the input signal having a potential approximately equal to or less than the first supply potential;
- and
- a well bias control circuit having an nwell terminal coupled to the nwell of the PMOS pull-up transistor and to a well drive transistor coupled between the first supply potential and the nwell terminal, the well drive transistor configured to couple the nwell terminal to the first supply potential in response to the input signal having a potential approximately equal to or less than the first supply potential.
4 more elements
An input/output (I/O) buffer having an input mode and coupled between first and second supply voltages, the input/output buffer comprising:
- an input/output node;
- an nwell;
- input means for receiving an input signal from the input node;
- pull-up means for coupling the first power supply voltage to the input/output node;
- pull-down means for coupling the second power supply voltage to the input/output node;
- gate bias control means for coupling a control terminal on the pull-up means to the input/output node in response to the input signal having a voltage greater than approximately the first supply voltage;
- passgate coupling means for coupling the control terminal of the pull-up means to the first supply voltage in response to the input signal having a voltage approximately equal to or less than the first supply voltage;
- and
- well bias control means for coupling the nwell to the first supply voltage in response to the input signal having a voltage approximately equal to or less than the first supply voltage and for increasing the potential on the nwell in response to the input signal having a voltage greater than approximately the first supply voltage.
6 more elements
An input/output (I/O) buffer having an input mode and coupled between first and second supply potentials, the input/output buffer comprising:
- an input/output node;
- a PMOS pull-up transistor having gate, source, drain and body terminals, and fabricated in an nwell, the source terminal coupled to the first supply potential and the drain terminal coupled to the input/output node;
- an NMOS pull-down transistor having source and drain terminals, the source terminal coupled to the second supply potential and the drain terminal coupled to the input/output node;
- a gate bias control transistor having gate, source, and drain terminals, the source terminal coupled to the input node, the drain coupled to the gate of the PMOS pull-up transistor, and the gate terminal coupled to the first supply potential and configured to couple the gate of the PMOS pull-up transistor to the input/output node in response to the input signal having a potential greater than approximately the first supply potential;
- a passgate having an NMOS passgate transistor and a PMOS passgate transistor, the NMOS passgate transistor and the PMOS passgate transistor each having source and drain terminals, the source terminals of each passgate transistor coupled to each other and to a circuit node with a potential configured to be approximately equal to the first supply potential during the input mode, and the drain terminals coupled to each other and to the gate of the PMOS pull-up transistor and configured to couple the gate of the PMOS pull-up transistor to the first supply potential in response to the input signal having a potential approximately equal to or less than the first supply potential;
- and
- a well bias control circuit having an nwell terminal coupled to the nwell of the PMOS pull-up transistor and to a well drive transistor coupled between the first supply potential and the nwell terminal, the well drive transistor configured to couple the nwell terminal to the first supply potential in response to the input signal having a potential approximately equal to or less than the first supply potential.
4 more elements
An integrated circuit including an input/output (I/O) buffer having an input mode and coupled between first and second supply potentials, the integrated circuit comprising:
- an integrated circuit core coupled to the input/output buffer;
- a pad coupled to the input/output buffer;
- the input/output buffer having:
- an input/output node;
- a PMOS pull-up transistor having gate, source, drain and body terminals, and fabricated in an nwell, the source terminal coupled to the first supply potential and the drain terminal coupled to the input/output node;
- an NMOS pull-down transistor having source and drain terminals, the source terminal coupled to the second supply potential and the drain terminal coupled to the input/output node;
- a gate bias control transistor having gate, source, and drain terminals, the source terminal coupled to the input node, the drain coupled to the gate of the PMOS pull-up transistor, and the gate terminal coupled to the first supply potential and configured to couple the gate of the PMOS pull-up transistor to the input/output node in response to the input signal having a potential greater than approximately the first supply potential;
- a passgate having an NMOS passgate transistor and a PMOS passgate transistor, the NMOS passgate transistor and the PMOS passgate transistor each having source and drain terminals, the source terminals of each passgate transistor coupled to each other and to a circuit node with a potential configured to be approximately equal to the first supply potential during the input mode, and the drain terminals coupled to each other and to the gate of the PMOS pull-up transistor and configured to couple the gate of the PMOS pull-up transistor to the first supply potential in response to the input signal having a potential approximately equal to or less than the first supply potential;
- and
- a well bias control circuit having an nwell terminal coupled to the nwell of the PMOS pull-up transistor and to a well drive transistor coupled between the first supply potential and the nwell terminal, the well drive transistor configured to couple the nwell terminal to the first supply potential in response to the input signal having a potential approximately equal to or less than the first supply potential.
7 more elements
Dependencies are inferred from the claim text.