# US 2006/0066342 A1 · Utilizing clock shield as defect monitor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2006/0066342 A1 - Document ID: US20060066342A1 - Status: Published application - Kind: A1 - Application number: 11/280,008 - Filed: 2005-11-16 - Published: 2006-03-30 - Earliest claimed: 2004-06-28 - Assignees: International Business Machines Corporation - Inventors: John Cohn; Leah Pastel; Thomas Sopchak; David Vallett - Web page: https://patentgrep.com/patent/US20060066342A1 ## CPC - G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)} - G01R 31/30: Marginal testing, e.g. by varying supply voltage (testing computers during standby operation or idle time G06F11/22) - G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)} - G01R 31/52: Testing for short-circuits, leakage current or ground faults - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller. ## Claims ### Claim 1 An integrated circuit having a shielded clock tree comprising: at least one clock signal buffer; clock signal wiring connected to said clock signal buffer; shielding adjacent said clock signal wiring; ground wiring connecting said shielding to a predetermined voltage; and switches in said ground wiring. ### Claim 2 (depends on 1) The integrated circuit in claim 1, wherein said switches are adapted to connect said shielding to said predetermined voltage during non-test operations and to selectively disconnect said shielding from said predetermined voltage during test operations. ### Claim 3 (depends on 1) The integrated circuit in claim 1, wherein said switches are individually controllable such that different portions of said shielded clock tree can be isolated during testing to locate defects. ### Claim 4 (depends on 1) The integrated circuit in claim 1, wherein said at least one clock signal buffer comprises a main clock signal buffer connected to a plurality of secondary clock signal buffers by said clock signal wiring. ### Claim 5 (depends on 1) The integrated circuit in claim 1, wherein said shielding comprises shield wires positioned adjacent and parallel to said clock signal wiring. ### Claim 6 (depends on 1) The integrated circuit in claim 1, wherein said predetermined voltage comprises a ground voltage level. ### Claim 7 (depends on 1) The integrated circuit in claim 1, wherein each of said switches is connected to a plurality of ground wires. ### Claim 8 A shielded clock tree within an integrated circuit, said shielded clock tree comprising: at least one clock signal buffer; at least one clock signal splitter connected to said clock signal buffer; clock signal wiring connecting said clock signal buffer to said clock signal splitter; shielding adjacent said clock signal wiring; ground wiring connecting said shielding to ground; and switches in said ground wiring, wherein said switches are connected to a test controller. ### Claim 9 (depends on 8) The shielded clock tree in claim 8, wherein said switches are adapted to connect said shielding to ground during non-test operations and to disconnect said shielding from ground during test operations under direction of said test controller. ### Claim 10 (depends on 8) The shielded clock tree in claim 8, wherein said switches are individually controllable such that different portions of said shielded clock tree can be isolated during testing to locate defects. ### Claim 11 (depends on 8) The shielded clock tree in claim 8, wherein said at least one clock signal buffer comprises a main clock signal buffer connected to a plurality of secondary clock signal buffers by said clock signal wiring. ### Claim 12 (depends on 8) The shielded clock tree in claim 8, wherein said shielding comprises shield wires positioned adjacent and parallel to said clock signal wiring. ### Claim 13 (depends on 8) The shielded clock tree in claim 8, wherein said ground comprises a predetermined voltage level. ### Claim 14 (depends on 8) The shielded clock tree in claim 8, wherein each of said switches is connected to a plurality of ground wires. ### Claim 15 An integrated circuit having a shielded clock tree comprising: at least one clock signal buffer; clock signal wiring connected to said clock signal buffer; shielding adjacent said clock signal wiring; ground wiring connecting said shielding to a predetermined voltage; and switches in said ground wiring, wherein said switches are connected to a test controller. ### Claim 16 (depends on 15) The integrated circuit in claim 15, wherein said switches are adapted to connect said shielding to said predetermined voltage during non-test operations and to selectively disconnect said shielding from said predetermined voltage during test operations. ### Claim 17 (depends on 15) The integrated circuit in claim 15, wherein said switches are individually controllable such that different portions of said shielded clock tree can be isolated during testing to locate defects. ### Claim 18 (depends on 15) The integrated circuit in claim 15, wherein said at least one clock signal buffer comprises a main clock signal buffer connected to a plurality of secondary clock signal buffers by said clock signal wiring. ### Claim 19 (depends on 15) The integrated circuit in claim 15, wherein said shielding comprises shield wires positioned adjacent and parallel to said clock signal wiring. ### Claim 20 (depends on 15) The integrated circuit in claim 15, wherein said predetermined voltage comprises a ground voltage level.