Fault dictionaries for integrated circuit yield and quality analysis methods and systems

A computer-implemented method, comprising:

• receiving a list of potential defects in an integrated circuit layout identified by using extraction rules derived at least partially from a set of design manufacturing rules, the design manufacturing rules comprising design parameters for manufacturing an integrated circuit;
• producing a set of test patterns by:
• (a) selecting from previously generated test patterns one or more test patterns that detect at least some of the identified potential defects;
• (b) generating one or more test patterns that explicitly target at least some of the identified potential defects;
• or both (a) and (b);
• and
• generating at least one fault dictionary indicative of one or more failing test responses to an associated test pattern and one or more potential defects respectively associated with the failing test responses.

A method of testing integrated circuits, comprising:

• determining a set of defect extraction rules at least partially derived from a first set of design manufacturing rules, the defect extraction rules defining plural subcategories of at least one category of potential defects identified by the design manufacturing rules;
• extracting potential defects by applying at least a subset of the defect extraction rules to an electronic description of the physical layout of an integrated circuit, the extracted potential defects falling into at least one of the subcategories;
• defining plural circuit tests that indicate the presence of potential defects in the manufactured integrated circuits, the circuit tests each comprising a set of circuit stimuli to be applied to manufactured integrated circuits containing the integrated circuit;
• and
• storing for at least a plurality of circuit tests, the potential defect or defects detected by the circuit test and failing test responses that, if observed, would indicate the presence of the potential defect or defects detected by the circuit test.

A computer-implemented method, comprising:

• receiving test-result information from tests of multiple integrated circuits, the test-result information comprising failing test responses associated with respective test patterns applied during the tests;
• using a fault dictionary to diagnose at least a portion of the test-result information in order to identify potential defects that may have caused one or more of the failing test responses;
• and
• using at least one of an incremental diagnosis or incremental simulation procedure to diagnose test-result information that was not diagnosable using the fault dictionary.