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US 2006/0066291 A1Published application
Test circuit for delay lock loops
AssigneeIntel Corporation
InventorsAkira Kakizawa, Mark Beiley, Mamun Rashid
Life of this patent
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Abstract
A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the input signal. The method further comprises generating a test output signal from the input signal and delay lock loop output signal indicative of a relationship between a transition on the input signal and a transition on delay lock loop output signal.
Claims24
An apparatus comprising:
- a delay lock loop circuit;
- a first input signal trace coupled to the delay lock loop circuit to provide a first input signal to the delay lock loop circuit;
- a first output signal trace coupled to the delay lock loop circuit to receive a first output signal from the delay lock loop circuit;
- first circuitry coupled to the first input signal trace, the first output signal trace and the delay lock loop circuit to generate a first test output signal on a first test output signal trace, the first test output signal indicative of a relationship between a first transition on the first input signal and a second transition on the first output signal;
- a second output signal trace coupled to the delay lock loop circuit to receive a second output signal from the delay lock loop circuit;
- second circuitry coupled to the first output signal trace, the second output signal trace and the delay lock loop circuit to generate a second test output signal on a second test output signal trace, the second test output signal indicative of a relationship between a third transition on the first output signal and a fourth transition on the second output signal;
- and
- wherein the first input signal trace and the first output signal trace are coupled to a first one or more delay cells of the delay lock loop circuit and the second output signal trace is coupled to a second one or more delay cells of the delay lock loop circuit.
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A system comprising:
- a semiconductor component including;
- a delay lock loop circuit;
- a first input signal trace coupled to the delay lock loop circuit to provide a first input signal to the delay lock loop circuit;
- a first output signal trace coupled to the delay lock loop circuit to receive a first output signal from the delay lock loop circuit;
- first circuitry coupled to the first input signal trace, the first output signal trace and the delay lock loop circuit to generate a first test output signal on a first test output signal trace, the first test output signal indicative of when the first input signal transitions relative to a transition on the first output signal trace;
- a second output signal trace coupled to the delay lock loop circuit to receive a second output signal from the delay lock loop circuit;
- second circuitry coupled to the first output signal trace, the second output signal trace and the delay lock loop circuit to generate a second test output signal on a second test output signal trace, the second test output signal indicative of a relationship between a third transition on the first output signal and a fourth transition on the second output signal;
- wherein the first input signal trace and the first output signal trace are coupled to a first one or more delay cells of the delay lock loop circuit and the second output signal trace is coupled to a second one or more delay cells of the delay lock loop circuit
- a mass storage device;
- and
- at least one bus coupled between the semiconductor component and the mass storage device to facilitate data exchange between the semiconductor component and the mass storage device.
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Dependencies are inferred from the claim text.